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FPGA and ASIC implementations of AES
K Gaj, P Chodowiec - Cryptographic engineering, 2009 - Springer
FPGA and ASIC Implementations of AES | SpringerLink Skip to main content Advertisement
Springer Nature Link Account Menu Find a journal Publish with us Track your research …
Springer Nature Link Account Menu Find a journal Publish with us Track your research …
A reconfigurable and compact subpipelined architecture for AES encryption and decryption
K Li, H Li, G Mund - EURASIP Journal on Advances in Signal Processing, 2023 - Springer
AES has been used in many applications to provide the data confidentiality. A new 32-bit
reconfigurable and compact architecture for AES encryption and decryption is presented …
reconfigurable and compact architecture for AES encryption and decryption is presented …
A quantum logic array microarchitecture: Scalable quantum data movement and computation
TS Metodi, DD Thaker, AW Cross… - 38th Annual IEEE …, 2005 - ieeexplore.ieee.org
Recent experimental advances have demonstrated technologies capable of supporting
scalable quantum computation. A critical next step is how to put those technologies together …
scalable quantum computation. A critical next step is how to put those technologies together …
On parallelization of high-speed processors for elliptic curve cryptography
K Jarvinen, J Skytta - IEEE Transactions on Very Large Scale …, 2008 - ieeexplore.ieee.org
This paper discusses parallelization of elliptic curve cryptography hardware accelerators
using elliptic curves over binary fields F 2m. Elliptic curve point multiplication, which is the …
using elliptic curves over binary fields F 2m. Elliptic curve point multiplication, which is the …
A new ASIC implementation of an advanced encryption standard (AES) crypto-hardware accelerator
Single-chip hardware implementation of Advanced Encryption Standard (AES) offers a low-
power and low-area design that is suitable for portable devices. It is widely applicable for …
power and low-area design that is suitable for portable devices. It is widely applicable for …
[HTML][HTML] Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5
In this paper, a new 32-bit ASIP-based crypto processor for AES, IDEA, and MD5 is
designed. The instruction-set consists of both general purpose and specific instructions for …
designed. The instruction-set consists of both general purpose and specific instructions for …
Novel reversible design of advanced encryption standard cryptographic algorithm for wireless sensor networks
The quantum of power consumption in wireless sensor nodes plays a vital role in power
management since more number of functional elements are integrated in a smaller space …
management since more number of functional elements are integrated in a smaller space …
Study of the AES realization method on the reconfigurable hardware
Y Zhu, H Zhang, Y Bao - 2013 International Conference on …, 2013 - ieeexplore.ieee.org
In order to improve the realization efficiency of AES encryption algorithm based on FPGA
and reduce hardware resource utilization. We give a reconfigurable implementation of AES …
and reduce hardware resource utilization. We give a reconfigurable implementation of AES …
FPGA implementation of AES-based crypto processor
Increased demand for data security is an undeniable fact. Towards achieving higher
security, cryptographic algorithms play an important role in the protection of data from …
security, cryptographic algorithms play an important role in the protection of data from …
[SÁCH][B] Applications of evolutionary computation to cryptology
S Picek - 2015 - repository.ubn.ru.nl
Untitled Page 1 Page 2 Page 3 Applications of Evolutionary Computation to Cryptology
Stjepan Picek Page 4 Copyright c Stjepan Picek, 2015 ISBN: 978-94-6295-238-6 IPA …
Stjepan Picek Page 4 Copyright c Stjepan Picek, 2015 ISBN: 978-94-6295-238-6 IPA …