Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …

The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors
(CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires …

Routing algorithms play a crucial role in the performance of Network-on-Chip (NoC)-based
Multi-Processor Systems-on-Chip (MPSoC). However, the selection of appropriate and …

Emerging on-chip communication technologies like wireless Networks-on-Chip (WiNoCs)
have been proposed as candidate solutions for addressing the scalability limitations of …

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC
(MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it …

To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

A novel routing algorithm, namely dynamic XY (DyXY) routing, is proposed for NoCs to
provide adaptive routing and ensure deadlock-free and livelock-free routing at the same …

Due to wire delay scalability and bandwidth limitations inherent in shared buses and
dedicated links, packet-switched on-chip interconnection networks are fast emerging as the …

Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex
on-chip communication problems. The lack of an unified representation of applications and …