Methods for fault tolerance in networks-on-chip

M Radetzki, C Feng, X Zhao, A Jantsch - ACM Computing Surveys …, 2013 - dl.acm.org
Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …

Silent data corruptions at scale

HD Dixit, S Pendharkar, M Beadon, C Mason… - arxiv preprint arxiv …, 2021 - arxiv.org
Silent Data Corruption (SDC) can have negative impact on large-scale infrastructure
services. SDCs are not captured by error reporting mechanisms within a Central Processing …

Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance

KA Bowman, JW Tschanz, NS Kim… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery
circuits to eliminate the clock frequency guardband from dynamic supply voltage (V CC) and …

[BOK][B] New methods of concurrent checking

M Goessel, V Ocheretny, E Sogomonyan, D Marienfeld - 2008 - books.google.com
Computers are everywhere around us. We, for example, as air passengers, car drivers,
laptop users with Internet connection, cell phone owners, hospital patients, inhabitants in the …

Facelift: Hiding and slowing down aging in multicores

A Tiwari, J Torrellas - 2008 41st IEEE/ACM International …, 2008 - ieeexplore.ieee.org
Processors progressively age during their service life due to normal workload activity. Such
aging results in gradually slower circuits. Anticipating this fact, designers add timing …

Underdesigned and opportunistic computing in presence of hardware variability

P Gupta, Y Agarwal, L Dolecek, N Dutt… - … on Computer-Aided …, 2012 - ieeexplore.ieee.org
Microelectronic circuits exhibit increasing variations in performance, power consumption,
and reliability parameters across the manufactured parts and across use of these parts over …

Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era

S Ghosh, K Roy - Proceedings of the IEEE, 2010 - ieeexplore.ieee.org
Variations in process parameters affect the operation of integrated circuits (ICs) and pose a
significant threat to the continued scaling of transistor dimensions. Such parameter …

An efficient method to identify critical gates under circuit aging

W Wang, Z Wei, S Yang, Y Cao - 2007 IEEE/ACM International …, 2007 - ieeexplore.ieee.org
Negative bias temperature instability (NBTI) is the leading factor of circuit performance
degradation. Due to its complex dependence on operating conditions, especially signal …

Trojan scanner: Detecting hardware trojans with rapid sem imaging combined with image processing and machine learning

N Vashistha, H Lu, Q Shi, MT Rahman… - … for Testing and …, 2018 - dl.asminternational.org
Hardware Trojans are malicious changes to the design of integrated circuits (ICs) at different
stages of the design and fabrication processes. Different approaches have been developed …

Extratime: Modeling and analysis of wearout due to transistor aging at microarchitecture-level

F Oboril, MB Tahoori - IEEE/IFIP International Conference on …, 2012 - ieeexplore.ieee.org
With shrinking feature sizes, transistor aging due to NBTI and HCI becomes a major
reliability challenge for microprocessors. These processes lead to increased gate delays …