Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …

This book targets engineers and researchers familiar with basic computer architecture
concepts who are interested in learning about on-chip networks. This work is designed to be …

With the emergence of many-core architectures, it is quite likely that multiple applications will
run concurrently on a system. Existing locally and globally adaptive routing algorithms …

This book targets engineers and researchers familiar with basic computer architecture
concepts who are interested in learning about on-chip networks. This work is designed to be …

Process scaling has given designers billions of transistors to work with. As feature sizes near
the atomic scale, extensive variation and wearout inevitably make margining uneconomical …

Aggressive transistor scaling continues to drive increasingly complex digital designs. The
large number of transistors available today enables the development of chip multiprocessors …

The prevalence of multicore architectures has accentuated the need for scalable cache
coherence solutions. Many of the proposed designs use a mix of 1-to-1, 1-to-many (1-to-M) …

Chip Multi-processor (CMP) architectures have become mainstream for designing
processors. With a large number of cores, Networks-on-Chip (NOCs) provide a scalable …

Networks-on-chip (NoCs) are emerging as the way to interconnect the processing cores and
the memory within a chip multiprocessor. As recent years have seen a significant increase in …

As the technology sizes of integrated circuits (ICs) scale down rapidly, current transistor
densities on chips dramatically increase. While nanometer feature sizes allow denser chip …