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Floating gate memory device with interpoly charge trap** structure
HT Lue - US Patent 8,068,370, 2011 - Google Patents
(51) Int. Cl. A charge trap** floating gate is described with asymmetric GIC I6/06(2006.01)
tunneling barriers. The memory cell includes a source region HOIL 29/788(2006.01) and a …
tunneling barriers. The memory cell includes a source region HOIL 29/788(2006.01) and a …
Methods of operating p-channel non-volatile memory devices
HT Lue - US Patent 7,636,257, 2009 - Google Patents
150 disposed above the tunneling dielectric layer. An upper insu lating layer is disposed
above the charge storage layer, and a gate is disposed above the upper insulating multi …
above the charge storage layer, and a gate is disposed above the upper insulating multi …
Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
HT Lue, SY Wang - US Patent 8,264,028, 2012 - Google Patents
(60) Provisional application No. 60/640.229, filed on Jan. 3, 2005, provisional application
No. 60/647,012, filed (57) ABSTRACT on Jan. 27, 2005, provisional application No. Memory …
No. 60/647,012, filed (57) ABSTRACT on Jan. 27, 2005, provisional application No. Memory …
Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
SY Wang, HT Lue - US Patent 7,642,585, 2010 - Google Patents
2005/0237815 A1 10, 2005 Lue et al. Buckley, J., et al.,“Engineering of Conduction band
Crested Bar 2005/023781.6 A1 10, 2005 Lue et al. riers' or Dielectric Constant Crested …
Crested Bar 2005/023781.6 A1 10, 2005 Lue et al. riers' or Dielectric Constant Crested …
Charge trap** memory cell with high speed erase
HT Lue, SC Lai - US Patent App. 11/845,276, 2009 - Google Patents
US20090039414A1 - Charge trap** memory cell with high speed erase - Google Patents
US20090039414A1 - Charge trap** memory cell with high speed erase - Google Patents …
US20090039414A1 - Charge trap** memory cell with high speed erase - Google Patents …
Method of forming non-volatile memory having charge trap layer with compositional gradient
M Balseanu, V Zubkov, LQ ** memory cell with high speed erase
SC Lai, HT Lue, CW Liao - US Patent 7,737,488, 2010 - Google Patents
US PATENT DOCUMENTS 6,885,044 B2 4/2005 Ding 6,888,750 B2 5/2005 Walker et al.
5,515,324 A 5, 1996 Tanaka et al. 6,897,533 B1 5/2005 Yang et al. 5,602,775 A 2, 1997 Vo …
5,515,324 A 5, 1996 Tanaka et al. 6,897,533 B1 5/2005 Yang et al. 5,602,775 A 2, 1997 Vo …
Silicon on insulator and thin film transistor bandgap engineered split gate memory
Jan. 3, 2006, now Pat. No. 7,315,474, application No.(74) Attorney, Agent, or Firm—
McClure, Qualey & 12/056,489, which is a continuation-in-part of Rodack, LLP application …
McClure, Qualey & 12/056,489, which is a continuation-in-part of Rodack, LLP application …