A survey of FPGA-based LDPC decoders
P Hailes, L Xu, RG Maunder… - … Surveys & Tutorials, 2015 - ieeexplore.ieee.org
Low-density parity check (LDPC) error correction decoders have become popular in
communications systems, as a benefit of their strong error correction performance and their …
communications systems, as a benefit of their strong error correction performance and their …
Pre-trained VGGNet architecture for remote-sensing image scene classification
The visual geometry group network (VGGNet) is used widely for image classification and
has proven to be very effective method. Most existing approaches use features of just one …
has proven to be very effective method. Most existing approaches use features of just one …
Channel Coding Towards 6G: Technical Overview and Outlook
Channel coding plays a pivotal role in ensuring reliable communication over wireless
channels. With the growing need for ultra-reliable communication in emerging wireless use …
channels. With the growing need for ultra-reliable communication in emerging wireless use …
Flexible high throughput QC-LDPC decoder with perfect pipeline conflicts resolution and efficient hardware utilization
VL Petrović, MM Marković… - … on Circuits and …, 2020 - ieeexplore.ieee.org
Modern communication standards, such as 5G new radio (5G NR), require a high speed
decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely …
decoder for highly irregular quasi-cyclic low density parity check (QC-LDPC) codes. A widely …
Syndrome-based min-sum vs OSD-0 decoders: FPGA implementation and analysis for quantum LDPC codes
Quantum processors need to improve their reliability to scale up the number of qubits and
increase the number of algorithms that can execute. To reduce the logical error rate of the …
increase the number of algorithms that can execute. To reduce the logical error rate of the …
Analysis and design of cost-effective, high-throughput LDPC decoders
This paper introduces a new approach to cost-effective, high-throughput hardware designs
for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective …
for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective …
An FPGA-based LDPC decoder with ultra-long codes for continuous-variable quantum key distribution
SS Yang, JQ Liu, ZG Lu, ZL Bai, XY Wang, YM Li - IEEE Access, 2021 - ieeexplore.ieee.org
In this paper, we propose a good decoding performance, low-complexity, and high-speed
decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum …
decoder architecture for ultra-long quasi-cyclic LDPC codes by using the layered sum …
A 2.0 Gb/s throughput decoder for QC-LDPC convolutional codes
This paper proposes a decoder architecture for low-density parity-check convolutional code
(LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code …
(LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code …
Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications
Information theory coding is an impressive and most celebrated field of research that has
spawned numerous extremely important solutions to the intractable problems of secure data …
spawned numerous extremely important solutions to the intractable problems of secure data …
A 3.0 Gb/s throughput hardware-efficient decoder for cyclically-coupled QC-LDPC codes
In this paper, we propose a new class of quasi-cyclic low-density parity-check (QC-LDPC)
codes, namely cyclically-coupled QC-LDPC (CC-QC-LDPC) codes, and their RAM-based …
codes, namely cyclically-coupled QC-LDPC (CC-QC-LDPC) codes, and their RAM-based …