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AttAcc! Unleashing the power of PIM for batched transformer-based generative model inference
The Transformer-based generative model (TbGM), comprising summarization (Sum) and
generation (Gen) stages, has demonstrated unprecedented generative performance across …
generation (Gen) stages, has demonstrated unprecedented generative performance across …
{ABACuS}:{All-Bank} Activation Counters for Scalable and Low Overhead {RowHammer} Mitigation
We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …
technique that performance-, energy-, and area-efficiently scales with worsening …
Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications
In computer architecture studies, simulators are crucial for design verification, reducing
research and development time and ensuring the high accuracy of verification results …
research and development time and ensuring the high accuracy of verification results …
Understanding the security benefits and overheads of emerging industry solutions to dram read disturbance
We present the first rigorous security, performance, energy, and cost analyses of the state-of-
the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …
the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …
Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance
We 1) present the first rigorous security, performance, energy, and cost analyses of the state-
of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …
of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …
Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance
A Olgun, F Bostanci, IE Yuksel, O Canpolat… - arxiv preprint arxiv …, 2025 - arxiv.org
Modern DRAM chips are subject to read disturbance errors. State-of-the-art read
disturbance mitigations rely on accurate and exhaustive characterization of the read …
disturbance mitigations rely on accurate and exhaustive characterization of the read …
A mess of memory system benchmarking, simulation and application profiling
The Memory stress (Mess) framework provides a unified view of the memory system
benchmarking, simulation and application profiling. The Mess benchmark provides a holistic …
benchmarking, simulation and application profiling. The Mess benchmark provides a holistic …
Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching
Large language models (LLMs) have emerged due to their capability to generate high-
quality content across diverse contexts. To reduce their explosively increasing demands for …
quality content across diverse contexts. To reduce their explosively increasing demands for …
Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing
(hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM …
(hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM …
Breakhammer: Enhancing rowhammer mitigations by carefully throttling suspect threads
RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing
(hammering) a row of DRAM cells (DRAM row) induces bitflips in other physically nearby …
(hammering) a row of DRAM cells (DRAM row) induces bitflips in other physically nearby …