AttAcc! Unleashing the power of PIM for batched transformer-based generative model inference

J Park, J Choi, K Kyung, MJ Kim, Y Kwon… - Proceedings of the 29th …, 2024 - dl.acm.org
The Transformer-based generative model (TbGM), comprising summarization (Sum) and
generation (Gen) stages, has demonstrated unprecedented generative performance across …

{ABACuS}:{All-Bank} Activation Counters for Scalable and Low Overhead {RowHammer} Mitigation

A Olgun, YC Tugrul, N Bostanci, IE Yuksel… - 33rd USENIX Security …, 2024 - usenix.org
We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …

Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications

I Hwang, J Lee, H Kang, G Lee, H Kim - Simulation Modelling Practice and …, 2024 - Elsevier
In computer architecture studies, simulators are crucial for design verification, reducing
research and development time and ensuring the high accuracy of verification results …

Understanding the security benefits and overheads of emerging industry solutions to dram read disturbance

O Canpolat, AG Yağlıkçı, GF Oliveira, A Olgun… - arxiv preprint arxiv …, 2024 - arxiv.org
We present the first rigorous security, performance, energy, and cost analyses of the state-of-
the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …

Chronus: Understanding and Securing the Cutting-Edge Industry Solutions to DRAM Read Disturbance

O Canpolat, AG Yağlıkçı, GF Oliveira, A Olgun… - arxiv preprint arxiv …, 2025 - arxiv.org
We 1) present the first rigorous security, performance, energy, and cost analyses of the state-
of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …

Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance

A Olgun, F Bostanci, IE Yuksel, O Canpolat… - arxiv preprint arxiv …, 2025 - arxiv.org
Modern DRAM chips are subject to read disturbance errors. State-of-the-art read
disturbance mitigations rely on accurate and exhaustive characterization of the read …

A mess of memory system benchmarking, simulation and application profiling

P Esmaili-Dokht, F Sgherzi, VS Girelli… - 2024 57th IEEE/ACM …, 2024 - ieeexplore.ieee.org
The Memory stress (Mess) framework provides a unified view of the memory system
benchmarking, simulation and application profiling. The Mess benchmark provides a holistic …

Duplex: A Device for Large Language Models with Mixture of Experts, Grouped Query Attention, and Continuous Batching

S Yun, K Kyung, J Cho, J Choi, J Kim… - 2024 57th IEEE/ACM …, 2024 - ieeexplore.ieee.org
Large language models (LLMs) have emerged due to their capability to generate high-
quality content across diverse contexts. To reduce their explosively increasing demands for …

Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions

YC Tuğrul, AG Yağlıkçı, İE Yüksel, A Olgun… - arxiv preprint arxiv …, 2025 - arxiv.org
RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing
(hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM …

Breakhammer: Enhancing rowhammer mitigations by carefully throttling suspect threads

O Canpolat, AG Yağlıkçı, A Olgun… - 2024 57th IEEE/ACM …, 2024 - ieeexplore.ieee.org
RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing
(hammering) a row of DRAM cells (DRAM row) induces bitflips in other physically nearby …