We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation
technique that performance-, energy-, and area-efficiently scales with worsening …

In computer architecture studies, simulators are crucial for design verification, reducing
research and development time and ensuring the high accuracy of verification results …

We present the first rigorous security, performance, energy, and cost analyses of the state-of-
the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …

The Memory stress (Mess) framework provides a unified view of the memory system
benchmarking, simulation and application profiling. The Mess benchmark provides a holistic …

We 1) present the first rigorous security, performance, energy, and cost analyses of the state-
of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting …

Modern DRAM chips are subject to read disturbance errors. State-of-the-art read
disturbance mitigations rely on accurate and exhaustive characterization of the read …

Large language models (LLMs) have emerged due to their capability to generate high-
quality content across diverse contexts. To reduce their explosively increasing demands for …

Transformers have revolutionized deep learning and generative modeling, enabling
advancements in natural language processing tasks. However, the size of transformer …

We propose a Mamba accelerator with reconfigurable architecture, MARCA. We propose
three novel approaches in this paper.(1) Reduction alternative PE array architecture for both …

RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing
(hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM …