Semiconductors, amongst one of the most important innovations of the 20 th century, have
played a pivotal role in the creation of a digitalized, modern industrial society. The global …

With the relentless scaling of technology nodes, design technology co-optimization (DTCO)
for the conventional (Conv.) cell structure is starting to reach its limitations due to limited …

In advanced nodes, scaling of critical dimension and pitch has not progressed at historical
Moore's Law rates. Thus, scaling boosters are explored to improve achievable power …

In this article, we propose an automated standard cell synthesis framework, SP&R, which
simultaneously solves P&R without deploying any sequential/separate operations, by a …

Complementary field-effect transistor (CFET) is a future transistor type with a high potential
to be used beyond 3-nm technology nodes. Despite its high future value, studies related to …

This paper surveys a number of noticeable recent research activities on the design and
technology co-optimization (DTCO) with multi-bit flip-flop cells in design automation …

As the technology node is evolving, standard cell (SDC) design scaling is obstructed by
design constraints such as limited routing resources, lateral PN separation, and …

With the relentless scaling of technology nodes, the track number reduction of conventional
(Conv.) cell is starting to reach its limitations due to limited routing resources, lateral pn …

As the layout of standard cells is becoming dense, accessing pins is much harder in detailed
routing. The conventional solutions to resolving the pin access issue are to attempt cell …

As technology nodes evolve, geometric pitch scaling starts to slow down. In order to retain
the trend of the Moore's Law, Design Technology Co-Optimization (DTCO) and System …