Turnitin
降AI改写
早检测系统
早降重系统
Turnitin-UK版
万方检测-期刊版
维普编辑部版
Grammarly检测
Paperpass检测
checkpass检测
PaperYY检测
Semiconductor packages and methods of forming the same
HW Chen, J Chen, DC Yeh, S Jeng, CH Yu - US Patent 9,735,129, 2017 - Google Patents
US9735129B2 - Semiconductor packages and methods of forming the same - Google Patents
US9735129B2 - Semiconductor packages and methods of forming the same - Google Patents …
US9735129B2 - Semiconductor packages and methods of forming the same - Google Patents …
Stacked semiconductor devices and methods of forming same
HW Chen, DC Yeh, L Huang - US Patent 10,163,661, 2018 - Google Patents
US10163661B2 - Stacked semiconductor devices and methods of forming same - Google
Patents US10163661B2 - Stacked semiconductor devices and methods of forming same …
Patents US10163661B2 - Stacked semiconductor devices and methods of forming same …
Structure design for 3DIC testing
JC Lin, PH Tsai - US Patent 9,219,016, 2015 - Google Patents
BACKGROUND In the packaging of integrated circuits, a plurality of pack age components
may be bundled in the same package. The package components may include device dies …
may be bundled in the same package. The package components may include device dies …
Packaging Structures and Methods
A package component is free from active devices therein. The package component includes
a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a …
a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a …
Packaging structures and methods with a metal pillar
A package component is free from active devices therein. The package component includes
a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a …
a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a …
Semiconductor device including a solder and method of fabricating the same
JY Myung, Y Kwon - US Patent 9,159,688, 2015 - Google Patents
(57) ABSTRACT A semiconductor device includes a bonding pad on a semi conductor
Substrate, a bump on the bonding pad, a solder on the bump, and an anti-wetting layer …
Substrate, a bump on the bonding pad, a solder on the bump, and an anti-wetting layer …
Zinc-cobalt barrier for interface in solder bond applications
N Dadvand, CD Manack, SF Pavone - US Patent 10,453,817, 2019 - Google Patents
A microelectronic device has bump bond structures on input/output (I/O) pads. The bump
bond structures include copper-containing pillars, a barrier layer including cobalt and zinc …
bond structures include copper-containing pillars, a barrier layer including cobalt and zinc …
Probe pad design for 3DIC package yield analysis
BACKGROUND In the packaging of integrated circuits, a plurality of pack age components
may be bundled in a same package. The package components may include device dies …
may be bundled in a same package. The package components may include device dies …
Nickel-tin microbump structures and method of making same
Techniques and mechanisms for providing effective connec tivity with surface level
microbumps on an integrated circuit package substrate. In an embodiment, different metals …
microbumps on an integrated circuit package substrate. In an embodiment, different metals …
Organic coating to inhibit solder wetting on pillar sidewalls
The present invention relates generally to and more particu larly, to a method of fabricating a
pillar interconnect structure with non-wettable sidewalls and the resulting structure. More …
pillar interconnect structure with non-wettable sidewalls and the resulting structure. More …