Bts: An accelerator for bootstrappable fully homomorphic encryption
Homomorphic encryption (HE) enables the secure offloading of computations to the cloud by
providing computation on encrypted data (ciphertexts). HE is based on noisy encryption …
providing computation on encrypted data (ciphertexts). HE is based on noisy encryption …
A detailed and flexible cycle-accurate network-on-chip simulator
Network-on-Chips (NoCs) are becoming integral parts of modern microprocessors as the
number of cores and modules integrated on a single chip continues to increase. Research …
number of cores and modules integrated on a single chip continues to increase. Research …
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip
communication was frequently ignored. This was because of fast, single-cycle on-chip …
communication was frequently ignored. This was because of fast, single-cycle on-chip …
A survey of on-chip optical interconnects
Numerous challenges present themselves when scaling traditional on-chip electrical
networks to large manycore processors. Some of these challenges include high latency …
networks to large manycore processors. Some of these challenges include high latency …
Slim fly: A cost effective low-diameter network topology
We introduce a high-performance cost-effective network topology called Slim Fly that
approaches the theoretically optimal network diameter. Slim Fly is based on graphs that …
approaches the theoretically optimal network diameter. Slim Fly is based on graphs that …
A case for bufferless routing in on-chip networks
T Moscibroda, O Mutlu - Proceedings of the 36th annual international …, 2009 - dl.acm.org
Buffers in on-chip networks consume significant energy, occupy chip area, and increase
design complexity. In this paper, we make a case for a new approach to designing on-chip …
design complexity. In this paper, we make a case for a new approach to designing on-chip …
Wireless NoC as interconnection backbone for multicore chips: Promises and challenges
Current commercial systems-on-chips (SoCs) designs integrate an increasingly large
number of predesigned cores and their number is predicted to increase significantly in the …
number of predesigned cores and their number is predicted to increase significantly in the …
Firefly: Illuminating future network-on-chip with nanophotonics
Future many-core processors will require high-performance yet energy-efficient on-chip
networks to provide a communication substrate for the increasing number of cores. Recent …
networks to provide a communication substrate for the increasing number of cores. Recent …
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs
An FPGA is a peculiar hardware realization substrate in terms of the relative speed and cost
of logic vs. wires vs. memory. In this paper, we present a Network-on-Chip (NoC) design …
of logic vs. wires vs. memory. In this paper, we present a Network-on-Chip (NoC) design …
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today's chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with
increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized …
increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized …