Towards evolvable systems based on the **linx Zynq platform
Field programmable gate arrays (FPGAs) are considered as a good platform for digital
evolvable hardware systems. Researchers introduced virtual reconfigurable circuits as the …
evolvable hardware systems. Researchers introduced virtual reconfigurable circuits as the …
Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware
J Wang, QS Chen, CH Lee - IET Computers & Digital Techniques, 2008 - IET
The authors present a novel virtual reconfigurable architecture (VRA) for realising real-world
applications of intrinsic evolvable hardware (EHW) on field programmable gate arrays …
applications of intrinsic evolvable hardware (EHW) on field programmable gate arrays …
An evolvable hardware system in **linx Virtex II Pro FPGA
In this paper, a new circuit architecture for image filter evolution is proposed. The evolvable
system is based on the implementation of a search algorithm in the PowerPC processor …
system is based on the implementation of a search algorithm in the PowerPC processor …
Image filter evolution on the **linx Zynq Platform
The limitations of reconfigurable chips have always raised barriers for evolvable hardware.
Zynq-7000 all programmable system-on-chip, the recent innovation in the reconfigurable …
Zynq-7000 all programmable system-on-chip, the recent innovation in the reconfigurable …
A bird's eye view of FPGA-based Evolvable Hardware
The Evolvable Hardware research area has achieved very important progresses in the last
two decades. However, it is still quite far from being as revolutionary as depicted in the …
two decades. However, it is still quite far from being as revolutionary as depicted in the …
Hardware accelerator of cartesian genetic programming with multiple fitness units
A new accelerator of Cartesian genetic programming is presented in this paper. The
accelerator is completely implemented in a single FPGA. The proposed architecture …
accelerator is completely implemented in a single FPGA. The proposed architecture …
On‐chip evolution of combinational logic circuits using an improved genetic‐simulated annealing algorithm
Q Shang, L Chen, P Peng - Concurrency and Computation …, 2020 - Wiley Online Library
This paper presents the on‐chip evolution system of combinational logic circuits by a new
hybrid algorithm known as improved genetic‐simulated annealing algorithm (IGASA). IGASA …
hybrid algorithm known as improved genetic‐simulated annealing algorithm (IGASA). IGASA …
An online EHW pattern recognition system applied to face image recognition
An evolvable hardware (EHW) architecture for high-speed pattern recognition has been
proposed. For a complex face image recognition task, the system demonstrates (in …
proposed. For a complex face image recognition task, the system demonstrates (in …
Online evolution for a high-speed image recognition system implemented on a Virtex-II Pro FPGA
Online incremental evolution for a complex high-speed pattern recognition architecture has
been implemented on a **linx Virtex-II Pro FPGA. The fitness evaluation module is entirely …
been implemented on a **linx Virtex-II Pro FPGA. The fitness evaluation module is entirely …
On the evolution of hardware circuits via reconfigurable architectures
Traditionally, hardware circuits are realized according to techniques that follow the classical
phases of design and testing. A completely new approach in the creation of hardware …
phases of design and testing. A completely new approach in the creation of hardware …