[BUKU][B] Handbook of signal processing systems

SS Bhattacharyya, EF Deprettere, R Leupers, J Takala - 2013 - Springer
In this new edition of the Handbook of Signal Processing Systems, many of the chapters
from the previous editions have been updated, and several new chapters have been added …

A hybrid systolic-dataflow architecture for inductive matrix algorithms

J Weng, S Liu, Z Wang, V Dadu… - 2020 IEEE International …, 2020 - ieeexplore.ieee.org
Dense linear algebra kernels are critical for wireless, and the oncoming proliferation of 5G
only amplifies their importance. Due to the inductive nature of many such algorithms …

Coarse-grained reconfigurable array architectures

BD Sutter, P Raghavan, A Lambrechts - Handbook of signal processing …, 2018 - Springer
Abstract Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same
inner loops that benefit from the high instruction-level parallelism (ILP) support in very long …

Chordmap: Automated map** of streaming applications onto cgra

Z Li, D Wijerathne, X Chen… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Streaming applications, consisting of several communicating kernels, are ubiquitous in the
embedded computing systems. The synchronous data flow (SDF) is commonly used to …

X-CGRA: An energy-efficient approximate coarse-grained reconfigurable architecture

O Akbari, M Kamal, A Afzali-Kusha… - … on Computer-Aided …, 2019 - ieeexplore.ieee.org
In this article, we present an energy-efficient approximate CGRA (X-CGRA). Instead of
conventional exact arithmetic units, it employs configurable approximate adders and …

Opencgra: Democratizing coarse-grained reconfigurable arrays

C Tan, NB Agostini, J Zhang, M Minutoli… - 2021 IEEE 32nd …, 2021 - ieeexplore.ieee.org
Reconfigurable architectures are today experiencing a renewed interest for their ability to
provide specialization without sacrificing the capability to adapt to disparate workloads …

Memory-aware loop map** on coarse-grained reconfigurable architectures

S Yin, X Yao, D Liu, L Liu, S Wei - IEEE Transactions on Very …, 2015 - ieeexplore.ieee.org
The coarse-grained reconfigurable architectures (CGRAs) are a promising class of
architectures with the advantages of high performance and high power efficiency. The …

Exploiting parallelism of imperfect nested loops on coarse-grained reconfigurable architectures

S Yin, X Lin, L Liu, S Wei - IEEE Transactions on Parallel and …, 2016 - ieeexplore.ieee.org
Coarse-grained reconfigurable architecture (CGRA) is a promising parallel computing
platform that provides high performance, high power efficiency and flexibility. However, for …

A Comprehensive Dataflow-Map** Optimization for Fully-Pipelined Execution in Spatial Programmable Architecture

P Liu, A Li, L Chen, J Jiang, Q Wang… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Although spatial programmable architectures have demonstrated high-performance and
programmability for a variety of applications, they suffer from the pipeline unbalancing issue …

Efficient execution of stream graphs on coarse-grained reconfigurable architectures

S Oh, H Lee, J Lee - … on Computer-Aided Design of Integrated …, 2017 - ieeexplore.ieee.org
Coarse-grained reconfigurable architectures (CGRAs) can provide extremely energy-
efficient acceleration for applications that are rich in arithmetic operations such as digital …