Exploring the performance of 3-D nanosheet FET in inversion and junctionless modes: Device and circuit-level analysis and comparison

VB Sreenivasulu, AK Neelam, SR Kola, J Singh… - IEEE …, 2023 - ieeexplore.ieee.org
In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and
junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In …

Impact of scaling on nanosheet FET and CMOS circuit applications

NA Kumari, VB Sreenivasulu… - ECS Journal of Solid State …, 2023 - iopscience.iop.org
In this paper, the impact of scaling on the gate all around the nanosheet field effect transistor
(GAA NSFET) is assessed in detail at sub-5-nm nodes for digital and analog/RF …

Vertical GeSn nanowire MOSFETs for CMOS beyond silicon

M Liu, Y Junk, Y Han, D Yang, JH Bae… - Communications …, 2023 - nature.com
The continued downscaling of silicon CMOS technology presents challenges for achieving
the required low power consumption. While high mobility channel materials hold promise for …

Common source amplifier and ring oscillator circuit performance optimization using multi-bridge channel FETs

VB Sreenivasulu, NA Kumari, V Lokesh… - ECS Journal of Solid …, 2023 - iopscience.iop.org
In this paper the DC, analog/RF device and circuit applications of nanosheet (NS) FET is
performed. To enhance power performance co-optimization geometry parameters like NS …

Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters

NA Kumari, P Prithvi - Microelectronics Journal, 2022 - Elsevier
In this paper, DC and analog/RF figures of merit (FOMs) for different geometrical variations
of the Gate all around (GAA) Nanosheet FET (NSFET) are computationally examined. For …

Performance analysis of gate-stack dual-material DG MOSFET using work-function modulation technique for lower technology nodes

SK Das, U Nanda, SM Biswal, CK Pandey, LI Giri - Silicon, 2022 - Springer
Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS
technology below 100 nm. These effects can be overcome by using gate and channel …

A comprehensive analysis and performance comparison of CombFET and NSFET for CMOS circuit applications

NA Kumari, P Prithvi - AEU-International Journal of Electronics and …, 2023 - Elsevier
The performance of comb-like channel field effect transistor (CombFET) and nanosheet FET
(NSFET) is addressed at both device and circuit levels at the 3-nm node. The CombFET is …

A comprehensive analysis of nanosheet FET and its CMOS circuit applications at elevated temperatures

NA Kumari, P Prithvi - Silicon, 2023 - Springer
Abstract The Nanosheet Field Effect Transistor (NSFET) has been shown to be a viable
candidate for sub-7-nm technology nodes. This paper assesses and compares the NSFET …

Analysis of total ionizing dose response of optimized fin geometry workfunction modulated SOI-FinFET

A Ray, A Naugarhiya, GP Mishra - Microelectronics Reliability, 2022 - Elsevier
The total ionizing dose (TID) response of SOI-FinFET with linear gate workfunction
modulation is presented and evaluated. The gate metal workfunction is linearly modulated …

[HTML][HTML] Impact of deep cryogenic temperatures on gate stack dual material DG MOSFET performance: analog and RF analysis

SK Das, SM Biswal, LI Giri, U Nanda - e-Prime-Advances in Electrical …, 2024 - Elsevier
By understanding the potential benefits of Gate Stack Dual Material double gate MOSFET
(DG MOSFET), this research aims to contribute to the investigation of its electrical …