[BOOK][B] Handbook of approximation algorithms and metaheuristics

TF Gonzalez - 2007 - taylorfrancis.com
Delineating the tremendous growth in this area, the Handbook of Approximation Algorithms
and Metaheuristics covers fundamental, theoretical topics as well as advanced, practical …

NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints

TC Chen, ZW Jiang, TC Hsu, HC Chen… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
In addition to wirelength, modern placers need to consider various constraints such as
preplaced blocks and density. We propose a high-quality analytical placement algorithm …

Kraftwerk2—A fast force-directed quadratic placement approach using an accurate net model

P Spindler, U Schlichtmann… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
The force-directed quadratic placer ldquoKraftwerk2, rdquo as described in this paper, is
based on two main concepts. First, the force that is necessary to distribute the modules on …

The ISPD2005 placement contest and benchmark suite

GJ Nam, CJ Alpert, P Villarrubia, B Winter… - Proceedings of the 2005 …, 2005 - dl.acm.org
Without the MCNC and ISPD98 benchmarks, it would arguably not have been possible for
the academic community to make consistent advances in physical design over the last …

Capo: robust and scalable open-source min-cut floorplacer

JA Roy, DA Papa, SN Adya, HH Chan, AN Ng… - Proceedings of the …, 2005 - dl.acm.org
In this invited note we describe Capo, an open-source software tool for cell placement,
mixed-size placement and floorplanning with emphasis on routability. Capo is among the …

Routability-driven macro placement with embedded cnn-based prediction model

YH Huang, Z **e, GQ Fang, TC Yu… - … , Automation & Test …, 2019 - ieeexplore.ieee.org
With the dramatic shrink of feature size and the advance of semiconductor technology
nodes, numerous and complicated design rules need to be followed, and a chip design can …

Routability-driven placement and white space allocation

C Li, M **e, CK Koh, J Cong… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
We present a two-stage congestion-driven placement flow. First, during each refinement
stage of our multilevel global placement framework, we replace cells based on the …

Chip Placement with Diffusion

V Lee, C Deng, L Elzeiny, P Abbeel… - arxiv preprint arxiv …, 2024 - arxiv.org
Macro placement is a vital step in digital circuit design that defines the physical location of
large collections of components, known as macros, on a 2-dimensional chip. The physical …

PeF: Poisson's equation-based large-scale fixed-outline floorplanning

X Li, K Peng, F Huang, W Zhu - IEEE Transactions on Computer …, 2022 - ieeexplore.ieee.org
Floorplanning is the first stage of VLSI physical design. An effective floorplanning engine
definitely has a positive impact on chip design speed, quality, and performance. In this …

Architecture and details of a high quality, large-scale analytical placer

AB Kahng, S Reda, Q Wang - ICCAD-2005. IEEE/ACM …, 2005 - ieeexplore.ieee.org
Modern design requirements have brought additional complexities to netlists and layouts.
Millions of components, whitespace resources, and fixed/movable blocks are just a few to …