[BOOK][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
Power minimization in IC design: Principles and applications
M Pedram - ACM Transactions on Design Automation of Electronic …, 1996 - dl.acm.org
Low power has emerged as a principal theme in today's electronics industry. The need for
low power has caused a major paradigm shift in which power dissipation is as important as …
low power has caused a major paradigm shift in which power dissipation is as important as …
[BOOK][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
Transition density: A new measure of activity in digital circuits
FN Najm - IEEE Transactions on Computer-Aided Design of …, 1993 - ieeexplore.ieee.org
Noting that a common element in most causes of runtime failure is the extent of circuit
activity, ie the rate at which its nodes are switching, the author proposes a measure of …
activity, ie the rate at which its nodes are switching, the author proposes a measure of …
[PDF][PDF] Transition density, a stochastic measure of activity in digital circuits
FN Najm - Proceedings of the 28th ACM/IEEE Design Automation …, 1991 - dl.acm.org
Reliability assessment is an important part of the design process of digital integrated circuits.
We observe that a common thread that runs through most causes of run-time failure is the …
We observe that a common thread that runs through most causes of run-time failure is the …
Constructive multi-phase test point insertion for scan-based BIST
N Tamarapalli, J Rajski - Proceedings International Test …, 1996 - ieeexplore.ieee.org
This paper presents a novel test point insertion technique which, unlike the previous ones, is
based on a constructive methodology. A divide and conquer approach is used to partition …
based on a constructive methodology. A divide and conquer approach is used to partition …
Probabilistic simulation for reliability analysis of CMOS VLSI circuits
FN Najm, R Burch, P Yang… - IEEE Transactions on …, 1990 - ieeexplore.ieee.org
A current-estimation approach to support the analysis of electromigration (EM) failures in
power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original …
power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original …
Power conscious CAD tools and methodologies: A perspective
Power consumption is rapidly becoming an area of growing concern in IC and system
design houses. Issues such as battery life, thermal limits, packaging constraints and cooling …
design houses. Issues such as battery life, thermal limits, packaging constraints and cooling …
[BOOK][B] Random testing of digital circuits: theory and applications
R David - 2020 - books.google.com
Page 1 Random Testing of Digital Circuits Theory and Applications O 10 7. boomd René
David Page 2 Page 3 Random Testing of Digital Circuits Page 4 Page 5 CRC) CRC Press …
David Page 2 Page 3 Random Testing of Digital Circuits Page 4 Page 5 CRC) CRC Press …
Error mitigation using approximate logic circuits: A comparison of probabilistic and evolutionary approaches
AJ Sanchez-Clemente, L Entrena… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
Technology scaling poses an increasing challenge to the reliability of digital circuits.
Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very …
Hardware redundancy solutions, such as triple modular redundancy (TMR), produce very …