A cache coherence protocol is a set of rules, which cache controllers in a system with
multiple cache memories must follow to maintain the consistency of data stored in the local …

The complexity of the instruction set of modern processors often leads to faults in the
microinstruction sequencing, and timing errors, which are difficult to detect with conventional …

In this paper, we present a formal model of a pipelined version of the DLX processor, and
verify the correct operation of the pipeline using a formal verification approach based series …

We present an algorithm for generating Chu space models of the behaviors of arbitrarily
complex non-iterated systems including those with N-type dependencies. The generated …

We present an algorithm for automatic generation of behavioral models of non-iterated
systems from a structural Verilog specification. The models are represented as Chu spaces …

The complexity of the instruction set of modern microprocessors often leads to faults in the
microinstruction sequencing and timing errors in the implementation of the processor …

Formal verification has become an integral part of the product development cycle leading to
a demand for powerful, yet easy to use tools, which conceal the complexity of the underlying …

Series-parallel poset verification is a powerful methodology for proving the design
correctness of complex systems and protocols. In this paper we use series-parallel posets to …

In this paper we present an algorithm for automatic extraction of system behavior from a
structural Verilog specification. The algorithm generates a series-parallel poset expression …

The increasing complexity of hardware systems necessitates the development of new
methods to test the correctness of their operation. Lately, Formal Verification has proven to …