Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-
around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects …

This article critically reviews the fabrication challenges, emerging materials (wafer, high-k
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …

A contact resistance () becomes a major parasitic resistance in highly scaled modern
semiconductor devices. A wrap-around contact (WAC) has been suggested as a promising …

In this article, a reliable static random access memory (SRAM) circuit design is proposed for
improved thermal and electrical performance at 5-nm technology nodes. The proposed …

For improving self-heating effects (SHEs) in gate-all-around metal-oxide-semiconductor field-
effect transistors (GAA MOSFETs), hetero-gate-dielectric (HGD) is utilized. The HGD consists …

In this article, structure optimization of high-k interfacial layer (IL), deposited between the
gate and the gate sidewall spacer, was performed in a 5-nm node nanosheet field-effect …

Vertically stacked horizontal nanosheet gate-all-around transistors seem to be one of the
viable solutions toward scaling down below sub-7nm technology nodes. In this work, we …

In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is
proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet …

In this article, a reliable drain-extended (De) fin-shaped field-effect transistor (DeFinFET)
with improved thermal performance and electrical performance is proposed for high-voltage …

Abstract Nanosheet Field Effect Transistor (NSFET) has emerged as a promising candidate
to replace FinFET devices at sub-7nm technology nodes and for different SoC applications …