Design methodology for voltage-scaled clock distribution networks
A low-voltage/swing clocking methodology is developed through both circuit and algorithmic
innovations. The primary objective is to significantly reduce the power consumed by the …
innovations. The primary objective is to significantly reduce the power consumed by the …
An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0 V
Level converting is increasingly difficult in ultra-low voltage circuits with the aggressive
scaling down of the input voltage. In this paper, we proposed a wide output range level …
scaling down of the input voltage. In this paper, we proposed a wide output range level …
Cost-efficient 3D integration to hinder reverse engineering during and after manufacturing
Reverse engineering (RE) attacks pose a serious threat to the semiconductor supply chain.
In this paper, we address this problem by proposing a design flow that leverages the unique …
In this paper, we address this problem by proposing a design flow that leverages the unique …
ST2 GPU: An Energy-Efficient GPU Design with Spatio-Temporal Shared-Thread Speculative Adders
Modern GPUs employ thousands of cores, yielding higher performance but also higher
power consumption. To meet performance targets while staying within a reasonable power …
power consumption. To meet performance targets while staying within a reasonable power …
Energy-efficient CMOS voltage level shifters with single- for multi-core applications
The never-ending demands for battery-powered applications are driven by technological
advances in the field of low power digital CMOS circuits. The voltage level shifters are …
advances in the field of low power digital CMOS circuits. The voltage level shifters are …
Low swing TSV signaling using novel level shifters with single supply voltage
Low swing TSV signaling is proposed for three-dimensional (3D) integrated circuits (ICs) to
reduce dynamic power consumption. Novel level shifters are designed to lower the voltage …
reduce dynamic power consumption. Novel level shifters are designed to lower the voltage …
Voltage-frequency domain optimization for energy-neutral wearable health devices
Wearable health and activity monitoring devices must minimize the battery charging and
replacement requirements to be practical. Numerous design techniques, such as power …
replacement requirements to be practical. Numerous design techniques, such as power …
Uncovering Latent Hardware/Software Parallelism
V Kandiah - 2023 - search.proquest.com
With the breakdown of Dennard Scaling, modern heterogeneous systems necessitate
parallelism at both the hardware and software layers to meet today's demands for …
parallelism at both the hardware and software layers to meet today's demands for …
[PDF][PDF] Computer Science Department
V Kandiah - 2023 - mccormick.northwestern.edu
With the breakdown of Dennard Scaling, modern heterogeneous systems necessitate
parallelism at both the hardware and software layers to meet today's demands for …
parallelism at both the hardware and software layers to meet today's demands for …
High Efficiency Fully Integrated On-Chip Regulator for Wide-Range Output Current
A novel regulator topology is proposed to achieve high power efficiency for a wide range of
output load current. The proposed topology consists of a switched-capacitor regulator and …
output load current. The proposed topology consists of a switched-capacitor regulator and …