Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems

W Wang, P Mishra, S Ranka - Proceedings of the 48th Design …, 2011 - dl.acm.org
Multicore architectures, especially chip multi-processors, have been widely acknowledged
as a successful design paradigm. Existing approaches primarily target application-driven …

Energy-aware real-time task scheduling in multiprocessor systems using a hybrid genetic algorithm

A Mahmood, SA Khan, F Albalooshi, N Awwad - Electronics, 2017 - mdpi.com
Minimizing power consumption to prolong battery life has become an important design issue
for portable battery-operated devices such as smartphones and personal digital assistants …

System-wide leakage-aware energy minimization using dynamic voltage scaling and cache reconfiguration in multitasking systems

W Wang, P Mishra - IEEE Transactions on Very Large Scale …, 2011 - ieeexplore.ieee.org
System optimization techniques are widely used to improve energy efficiency as well as
overall performance. Dynamic voltage scaling (DVS) is well studied and known to be …

Optimizing the NoC slack through voltage and frequency scaling in hard real-time embedded systems

J Zhan, N Stoimenov, J Ouyang, L Thiele… - … on Computer-Aided …, 2014 - ieeexplore.ieee.org
Hard real-time embedded systems impose a strict latency requirement on interconnection
subsystems. In the case of network-on-chip (NoC), this means each packet of a traffic stream …

[BOOK][B] Dynamic Reconfiguration in Real-Time Systems

W Wang, P Mishra, S Ranka - 2012 - Springer
Computing has transformed humankind. General-purpose computers such as desktops and
laptops are used by a larger fraction of the world population. However, in many scenarios …

Instruction-cycle-based dynamic voltage scaling power management for low-power digital signal processor with 53% power savings

SY Peng, TC Huang, YH Lee, CC Chiu… - IEEE Journal of Solid …, 2013 - ieeexplore.ieee.org
This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage
scaling (iDVS) power management strategy for low-power processor designs. The proposed …

Proactive thermal management using memory-based computing in multicore architectures

S Charles, H Hajimiri, P Mishra - 2018 Ninth International …, 2018 - ieeexplore.ieee.org
Reliability is a major concern in modern electronic systems due to high defect rates and
large parametric variations. A major contributor to reliability concerns is the potential thermal …

Energy-aware dynamic slack allocation for real-time multitasking systems

W Wang, S Ranka, P Mishra - Sustainable Computing: Informatics and …, 2012 - Elsevier
Dynamic voltage scaling (DVS) has been a very effective technique for processor energy
reduction. It adjusts processor voltage and frequency level during runtime. In this article, we …

Dynamic scheduling of tasks for multi‐core real‐time systems based on optimum energy and throughput

K Baital, A Chakrabarti - IET Computers & Digital Techniques, 2019 - Wiley Online Library
One of the critical design issues in real‐time systems is energy consumption, especially in
battery‐operated systems. Generally higher processor voltage generates higher throughput …

Reactive rejuvenation of CMOS logic paths using self-activating voltage domains

RA Ashraf, A Al-Zahrani, N Khoshavi… - … on Circuits and …, 2015 - ieeexplore.ieee.org
Although the trend of technology scaling is sought to realize higher performance computer
systems, it also results in Integrated Circuits (ICs) suffering from increasing Process, Voltage …