An overview of efficient interconnection networks for deep neural network accelerators

SM Nabavinejad, M Baharloo, KC Chen… - IEEE Journal on …, 2020 - ieeexplore.ieee.org
Deep Neural Networks (DNNs) have shown significant advantages in many domains, such
as pattern recognition, prediction, and control optimization. The edge computing demand in …

DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks

GF Oliveira, J Gómez-Luna, L Orosa, S Ghose… - IEEE …, 2021 - ieeexplore.ieee.org
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …

Kunpeng 920: The first 7-nm chiplet-based 64-core arm soc for cloud services

J **a, C Cheng, X Zhou, Y Hu, P Chun - IEEE Micro, 2021 - ieeexplore.ieee.org
Kunpeng 920 is the second generation server processor designed by HiSilicon based on
ARM architecture. Kunpeng 920 is able to achieve cost efficiency for various workloads …

[PDF][PDF] Research problems and opportunities in memory systems

O Mutlu, L Subramanian - Supercomputing frontiers and …, 2014 - superfri.susu.ru
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

Problems and challenges of emerging technology networks− on− chip: A review

AB Achballah, SB Othman, SB Saoud - Microprocessors and Microsystems, 2017 - Elsevier
Abstract Networks− on− chip (NoC) are an alternative to alleviate the problems of legacy
interconnect fabrics. However, many emerging technology NoC are developed and are now …

Nord: Node-router decoupling for effective power-gating of on-chip routers

L Chen, TM Pinkston - 2012 45th Annual IEEE/ACM …, 2012 - ieeexplore.ieee.org
While power-gating is a promising technique to mitigate the increasing static power of a
chip, a fundamental requirement is for the idle periods to be sufficiently long to compensate …

[Књига][B] Efficient microarchitecture for network-on-chip routers

DU Becker - 2012 - search.proquest.com
Continuing advances in semiconductor technology, coupled with an increasing concern for
energy efficiency, have led to an industry-wide shift in focus towards modular designs that …

Power punch: Towards non-blocking power-gating of noc routers

L Chen, D Zhu, M Pedram… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
As chip designs penetrate further into the dark silicon era, innovative techniques are much
needed to power off idle or under-utilized system components while having minimal impact …

MinBD: Minimally-buffered deflection routing for energy-efficient interconnect

C Fallin, G Nazario, X Yu, K Chang… - 2012 IEEE/ACM …, 2012 - ieeexplore.ieee.org
A conventional Network-on-Chip (NoC) router uses input buffers to store in-flight packets.
These buffers improve performance, but consume significant power. It is possible to bypass …

On-chip networks from a networking perspective: Congestion and scalability in many-core interconnects

GP Nychis, C Fallin, T Moscibroda, O Mutlu… - ACM SIGCOMM …, 2012 - dl.acm.org
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network
design, highlighting similarities and differences between the two. As an initial case study, we …