McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures

S Li, JH Ahn, RD Strong, JB Brockman… - Proceedings of the …, 2009 - dl.acm.org
This paper introduces McPAT, an integrated power, area, and timing modeling framework
that supports comprehensive design space exploration for multicore and manycore …

Wattch: A framework for architectural-level power analysis and optimizations

D Brooks, V Tiwari, M Martonosi - ACM SIGARCH Computer Architecture …, 2000 - dl.acm.org
Power dissipation and thermal issues are increasingly significant in modern processors. As
a result, it is crucial that power/performance tradeoffs be made more visible to chip architects …

Design space exploration for 3D architectures

Y **e, GH Loh, B Black, K Bernstein - ACM Journal on Emerging …, 2006 - dl.acm.org
As technology scales, interconnects have become a major performance bottleneck and a
major source of power consumption for microprocessors. Increasing interconnect costs …

[LIBRO][B] Three-dimensional integrated circuit design

VF Pavlidis, I Savidis, EG Friedman - 2017 - books.google.com
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more
than twice as much new content, adding the latest developments in circuit models …

Energy efficient computing systems: Architectures, abstractions and modeling to techniques and standards

R Muralidhar, R Borovica-Gajic, R Buyya - ACM Computing Surveys …, 2022 - dl.acm.org
Computing systems have undergone a tremendous change in the last few decades with
several inflexion points. While Moore's law guided the semiconductor industry to cram more …

Clock rate versus IPC: The end of the road for conventional microarchitectures

V Agarwal, MS Hrishikesh, SW Keckler… - Proceedings of the 27th …, 2000 - dl.acm.org
The doubling of microprocessor performance every three years has been the result of two
factors: more transistors per chip and superlinear scali ng of the processor clock with …

Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems

R Ausavarungnirun, KKW Chang… - ACM SIGARCH …, 2012 - dl.acm.org
When multiple processor (CPU) cores and a GPU integrated together on the same chip
share the off-chip main memory, requests from the GPU can heavily interfere with requests …

Simultaneous multithreading: A platform for next-generation processors

SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm… - IEEE micro, 1997 - ieeexplore.ieee.org
Simultaneous multithreading is a processor design which consumes both thread-level and
instruction-level parallelism. In SMT processors, thread-level parallelism can come from …

The McPAT framework for multicore and manycore architectures: Simultaneously modeling power, area, and timing

S Li, JH Ahn, RD Strong, JB Brockman… - ACM Transactions on …, 2013 - dl.acm.org
This article introduces McPAT, an integrated power, area, and timing modeling framework
that supports comprehensive design space exploration for multicore and manycore …

Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams

MB Taylor, W Lee, J Miller, D Wentzlaff, I Bratt… - ACM SIGARCH …, 2004 - dl.acm.org
This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a
general-purpose architecture that performswell on a larger class of stream and embedded …