McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures
This paper introduces McPAT, an integrated power, area, and timing modeling framework
that supports comprehensive design space exploration for multicore and manycore …
that supports comprehensive design space exploration for multicore and manycore …
Wattch: A framework for architectural-level power analysis and optimizations
Power dissipation and thermal issues are increasingly significant in modern processors. As
a result, it is crucial that power/performance tradeoffs be made more visible to chip architects …
a result, it is crucial that power/performance tradeoffs be made more visible to chip architects …
Design space exploration for 3D architectures
As technology scales, interconnects have become a major performance bottleneck and a
major source of power consumption for microprocessors. Increasing interconnect costs …
major source of power consumption for microprocessors. Increasing interconnect costs …
[LIBRO][B] Three-dimensional integrated circuit design
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more
than twice as much new content, adding the latest developments in circuit models …
than twice as much new content, adding the latest developments in circuit models …
Energy efficient computing systems: Architectures, abstractions and modeling to techniques and standards
Computing systems have undergone a tremendous change in the last few decades with
several inflexion points. While Moore's law guided the semiconductor industry to cram more …
several inflexion points. While Moore's law guided the semiconductor industry to cram more …
Clock rate versus IPC: The end of the road for conventional microarchitectures
V Agarwal, MS Hrishikesh, SW Keckler… - Proceedings of the 27th …, 2000 - dl.acm.org
The doubling of microprocessor performance every three years has been the result of two
factors: more transistors per chip and superlinear scali ng of the processor clock with …
factors: more transistors per chip and superlinear scali ng of the processor clock with …
Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems
When multiple processor (CPU) cores and a GPU integrated together on the same chip
share the off-chip main memory, requests from the GPU can heavily interfere with requests …
share the off-chip main memory, requests from the GPU can heavily interfere with requests …
Simultaneous multithreading: A platform for next-generation processors
Simultaneous multithreading is a processor design which consumes both thread-level and
instruction-level parallelism. In SMT processors, thread-level parallelism can come from …
instruction-level parallelism. In SMT processors, thread-level parallelism can come from …
The McPAT framework for multicore and manycore architectures: Simultaneously modeling power, area, and timing
This article introduces McPAT, an integrated power, area, and timing modeling framework
that supports comprehensive design space exploration for multicore and manycore …
that supports comprehensive design space exploration for multicore and manycore …
Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams
This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a
general-purpose architecture that performswell on a larger class of stream and embedded …
general-purpose architecture that performswell on a larger class of stream and embedded …