T-CREST: Time-predictable multi-core architecture for embedded systems
Real-time systems need time-predictable platforms to allow static analysis of the worst-case
execution time (WCET). Standard multi-core processors are optimized for the average case …
execution time (WCET). Standard multi-core processors are optimized for the average case …
Argo: A real-time network-on-chip architecture with an efficient GALS implementation
In this paper, we present an area-efficient, globally asynchronous, locally synchronous
network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC …
network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC …
Computing accurate performance bounds for best effort networks-on-chip
Real-time (RT) communication support is a critical requirement for many complex embedded
applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper …
applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper …
Congestion aware low power on chip protocols with network on chip with cloud security
This article is to analyze the bottleneck problems of NoC in many more applications like
multi-processor communication, computer architectures, and network interface processors …
multi-processor communication, computer architectures, and network interface processors …
Buffer space allocation for real-time priority-aware networks
In this work, we address the challenge of incorporating buffer space constraints in worst-
case latency analysis for priority-aware networks. A priority-aware network is a wormhole …
case latency analysis for priority-aware networks. A priority-aware network is a wormhole …
Delay analysis of wormhole based heterogeneous NoC
We introduce a novel evaluation methodology to analyze the delay of a wormhole routing
based NoC with variable link capacities and a variable number of virtual channels per link …
based NoC with variable link capacities and a variable number of virtual channels per link …
Performance evaluation and design tradeoffs of on-chip interconnect architectures
Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to
achieve high-performance and scalability in System-on-Chip (SoC) design. Performance …
achieve high-performance and scalability in System-on-Chip (SoC) design. Performance …
An accurate and scalable analytic model for round-robin arbitration in network-on-chip
E Fischer, GP Fettweis - 2013 Seventh IEEE/ACM International …, 2013 - ieeexplore.ieee.org
Due to continuously increasing performance requirements of embedded applications,
today's multi-processor system-on-chips will evolve towards many-core system-on-chips …
today's multi-processor system-on-chips will evolve towards many-core system-on-chips …
Analytical modeling and evaluation of network-on-chip architectures
Network-on-chip (NoC) architectures adopted for System-on-Chip (SoC) are characterized
by different trade-offs between latency, throughput, communication load, energy …
by different trade-offs between latency, throughput, communication load, energy …
Extending Network Calculus to Deal with Min-Plus Service Curves in Multiple Flow Scenarios
Network Calculus (NC) is a versatile analytical methodology to efficiently compute
performance bounds in networked real-time systems. The arrival and service curve …
performance bounds in networked real-time systems. The arrival and service curve …