T-CREST: Time-predictable multi-core architecture for embedded systems

M Schoeberl, S Abbaspour, B Akesson… - Journal of Systems …, 2015 - Elsevier
Real-time systems need time-predictable platforms to allow static analysis of the worst-case
execution time (WCET). Standard multi-core processors are optimized for the average case …

Argo: A real-time network-on-chip architecture with an efficient GALS implementation

E Kasapaki, M Schoeberl, RB Sørensen… - … Transactions on Very …, 2015 - ieeexplore.ieee.org
In this paper, we present an area-efficient, globally asynchronous, locally synchronous
network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC …

Computing accurate performance bounds for best effort networks-on-chip

D Rahmati, S Murali, L Benini… - IEEE Transactions …, 2011 - ieeexplore.ieee.org
Real-time (RT) communication support is a critical requirement for many complex embedded
applications which are currently targeted to Network-on-chip (NoC) platforms. In this paper …

Congestion aware low power on chip protocols with network on chip with cloud security

S Ponnan, TA Kumar, H Vs, S Natarajan… - Journal of Cloud …, 2022 - Springer
This article is to analyze the bottleneck problems of NoC in many more applications like
multi-processor communication, computer architectures, and network interface processors …

Buffer space allocation for real-time priority-aware networks

H Kashif, H Patel - 2016 IEEE Real-Time and Embedded …, 2016 - ieeexplore.ieee.org
In this work, we address the challenge of incorporating buffer space constraints in worst-
case latency analysis for priority-aware networks. A priority-aware network is a wormhole …

Delay analysis of wormhole based heterogeneous NoC

Y Ben-Itzhak, I Cidon, A Kolodny - Proceedings of the Fifth ACM/IEEE …, 2011 - dl.acm.org
We introduce a novel evaluation methodology to analyze the delay of a wormhole routing
based NoC with variable link capacities and a variable number of virtual channels per link …

Performance evaluation and design tradeoffs of on-chip interconnect architectures

M Bakhouya, S Suboh, J Gaber, T El-Ghazawi… - … Modelling Practice and …, 2011 - Elsevier
Network-on-Chip (NoC) has been proposed as an alternative to bus-based schemes to
achieve high-performance and scalability in System-on-Chip (SoC) design. Performance …

An accurate and scalable analytic model for round-robin arbitration in network-on-chip

E Fischer, GP Fettweis - 2013 Seventh IEEE/ACM International …, 2013 - ieeexplore.ieee.org
Due to continuously increasing performance requirements of embedded applications,
today's multi-processor system-on-chips will evolve towards many-core system-on-chips …

Analytical modeling and evaluation of network-on-chip architectures

S Suboh, M Bakhouya, J Gaber… - … Conference on High …, 2010 - ieeexplore.ieee.org
Network-on-chip (NoC) architectures adopted for System-on-Chip (SoC) are characterized
by different trade-offs between latency, throughput, communication load, energy …

Extending Network Calculus to Deal with Min-Plus Service Curves in Multiple Flow Scenarios

A Hamscher, VC Constantin… - 2024 IEEE 30th Real …, 2024 - ieeexplore.ieee.org
Network Calculus (NC) is a versatile analytical methodology to efficiently compute
performance bounds in networked real-time systems. The arrival and service curve …