FPGA dynamic and partial reconfiguration: A survey of architectures, methods, and applications
Dynamic and partial reconfiguration are key differentiating capabilities of field
programmable gate arrays (FPGAs). While they have been studied extensively in academic …
programmable gate arrays (FPGAs). While they have been studied extensively in academic …
Modern development methods and tools for embedded reconfigurable systems: A survey
Heterogeneous reconfigurable systems provide drastically higher performance and lower
power consumption than traditional CPU-centric systems. Moreover, they do it at much lower …
power consumption than traditional CPU-centric systems. Moreover, they do it at much lower …
Run-time partial reconfiguration speed investigation and architectural design space exploration
Run-time partial reconfiguration (PR) speed is significant in applications especially when
fast IP core switching is required. In this paper, we propose to use direct memory access …
fast IP core switching is required. In this paper, we propose to use direct memory access …
Modular dynamic reconfiguration in Virtex FPGAs
P Sedcole, B Blodget, T Becker, J Anderson… - … -Computers and Digital …, 2006 - IET
Modular systems implemented on field-programmable gate arrays (FPGAs) can benefit from
being able to load and unload modules at run-time, a concept that is of much interest in the …
being able to load and unload modules at run-time, a concept that is of much interest in the …
Dynamic and partial FPGA exploitation
J Becker, M Hubner, G Hettich… - Proceedings of the …, 2007 - ieeexplore.ieee.org
Today's field programmable gate array (FPGA) architectures, like **linx's Virtex-II series,
enable partial and dynamic run-time self-reconfiguration. This feature allows the substitution …
enable partial and dynamic run-time self-reconfiguration. This feature allows the substitution …
Enhancing relocatability of partial bitstreams for run-time reconfiguration
This paper introduces a method that enhances the relocatability of partial bitstreams for
FPGA run-time reconfiguration. Reconfigurable applications usually employ partial …
FPGA run-time reconfiguration. Reconfigurable applications usually employ partial …
Applying partial reconfiguration to networks-on-chips
T Pionteck, R Koch, C Albrecht - 2006 International Conference …, 2006 - ieeexplore.ieee.org
This paper presents CoNoChi, an adaptable network-on-chip for dynamically reconfigurable
hardware designs. CoNoChi is designed for taking advantage of the partial dynamic …
hardware designs. CoNoChi is designed for taking advantage of the partial dynamic …
Deriving an NCD file from an FPGA bitstream: Methodology, architecture and evaluation
Z Ding, Q Wu, Y Zhang, L Zhu - Microprocessors and Microsystems, 2013 - Elsevier
This paper demonstrates a reverse engineering method that takes a bitstream as input and
produces an NCD (Native Circuit Description) file for a **linx FPGA chip. The work can be …
produces an NCD (Native Circuit Description) file for a **linx FPGA chip. The work can be …
Logic chip, logic system and method for designing a logic chip
(57) ABSTRACT A logic chip has a plurality of individually addressable resource blocks
each of the resource blocks having logic circuitry, and a communication bar extending …
each of the resource blocks having logic circuitry, and a communication bar extending …
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
C Claus, FH Muller, J Zeppenfeld… - 2007 IEEE International …, 2007 - ieeexplore.ieee.org
The **linx Virtex family of FPGAs provides the ability to perform partial run-time
reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept …
reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept …