Predicting application run times using historical information
We present a technique for deriving predictions for the run times of parallel applications from
the run times of “similar” applications that have executed in the past. The novel aspect of our …
the run times of “similar” applications that have executed in the past. The novel aspect of our …
Recent developments in high-level synthesis
YL Lin - ACM Transactions on Design Automation of Electronic …, 1997 - dl.acm.org
We survey recent developments in high level synthesis technology for VLSI design. The
need for higher-level design automation tools are discussed first. We then describe some …
need for higher-level design automation tools are discussed first. We then describe some …
[BOOK][B] SPARK: a parallelizing approach to the high-level synthesis of digital circuits
Rapid advances in microelectronic integration and the advent of Systems-on-Chip have
fueled the need for high-level synthesis, ie, an automated approach to the synthesis of …
fueled the need for high-level synthesis, ie, an automated approach to the synthesis of …
Coordinated parallelizing compiler optimizations and high-level synthesis
We present a high-level synthesis methodology that applies a coordinated set of coarse-
grain and fine-grain parallelizing transformations. The transformations are applied both …
grain and fine-grain parallelizing transformations. The transformations are applied both …
Efficient scheduling of conditional behaviors for high-level synthesis
AA Kountouris, C Wolinski - ACM Transactions on Design Automation of …, 2002 - dl.acm.org
As hardware designs get increasingly complex and time-to-market constraints get tighter
there is strong motivation for high-level synthesis (HLS). HLS must efficiently handle both …
there is strong motivation for high-level synthesis (HLS). HLS must efficiently handle both …
Using global code motions to improve the quality of results for high-level synthesis
The quality of synthesis results for most high-level synthesis approaches is strongly affected
by the choice of control flow (through conditions and loops) in the input description. This …
by the choice of control flow (through conditions and loops) in the input description. This …
Improving evolutionary exploration to area-time optimization of FPGA designs
This paper presents a new methodology based on evolutionary multi-objective optimization
(EMO) to synthesize multiple complex modules on reprogrammable devices. It starts from a …
(EMO) to synthesize multiple complex modules on reprogrammable devices. It starts from a …
Wavesched: A novel scheduling technique for control-flow intensive designs
G Lakshminarayana, KS Khouri… - IEEE Transactions on …, 1999 - ieeexplore.ieee.org
In this paper, we present a novel scheduling algorithm targeted toward minimizing the
average execution time of control-flow intensive behavioral descriptions. Our algorithm uses …
average execution time of control-flow intensive behavioral descriptions. Our algorithm uses …
[BOOK][B] Scheduling techniques for high-throughput loop accelerators
F Hannig - 2009 - cs12.tf.fau.de
The desire for more mobility and the enthusiasm for ubiquitous electronic gadgets on the
one hand side and the steady progress in semiconductor industry on the other hand are the …
one hand side and the steady progress in semiconductor industry on the other hand are the …
High-level synthesis of low-power control-flow intensive circuits
KS Khouri, G Lakshminarayana… - IEEE Transactions on …, 1999 - ieeexplore.ieee.org
In this paper, we present a comprehensive high-level synthesis system that is geared toward
reducing power consumption in control-flow intensive as well as data-dominated circuits. An …
reducing power consumption in control-flow intensive as well as data-dominated circuits. An …