Systolic disaggregation within a matrix accelerator architecture
P Surti, S Maiyuran, V Andrei, A Appu… - US Patent …, 2024 - Google Patents
Embodiments described herein include software, firmware, and hardware logic that provides
techniques to perform arithmetic on sparse data via a systolic processing unit. One …
techniques to perform arithmetic on sparse data via a systolic processing unit. One …
Graphics processor operation scheduling for deterministic latency
J Ray, S Panneer, S Tangri, B Ashbaugh… - US Patent …, 2024 - Google Patents
Embodiments described herein include software, firmware, and hardware that provides
techniques to enable deterministic scheduling across multiple general-purpose graphics …
techniques to enable deterministic scheduling across multiple general-purpose graphics …
Systems and methods for cache optimization
A Koker, J Ray, E Ould-Ahmed-Vall, A Appu… - US Patent …, 2024 - Google Patents
Abstract Systems and methods for improving cache efficiency and utilization are disclosed.
In one embodiment, a graphics processor includes processing resources to perform …
In one embodiment, a graphics processor includes processing resources to perform …
Systems and methods for cache optimization
A Koker, J Ray, E Ould-Ahmed-Vall, A Appu… - US Patent …, 2024 - Google Patents
Abstract Systems and methods for improving cache efficiency and utilization are disclosed.
In one embodiment, a graphics processor includes processing resources to perform …
In one embodiment, a graphics processor includes processing resources to perform …
Instructions and logic to perform floating point and integer operations for machine learning
One embodiment provides for a graphics processing unit to accelerate machine-learning
operations, the graphics processing unit comprising a multiprocessor having a single …
operations, the graphics processing unit comprising a multiprocessor having a single …
Multi-tile architecture for graphics operations
A Koker, B Ashbaugh, S Janus… - US Patent …, 2024 - Google Patents
Embodiments are generally directed to a multi-tile architecture for graphics operations. An
embodiment of an apparatus includes a multi-tile architecture for graphics operations …
embodiment of an apparatus includes a multi-tile architecture for graphics operations …
Systems and methods for improving cache efficiency and utilization
A Koker, J Ray, B Ashbaugh, J Pearce… - US Patent App. 17 …, 2022 - Google Patents
2022-03-18 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Multi-tile memory management
AR Appu, A Koker, A Anantaraman… - US Patent …, 2024 - Google Patents
Methods and apparatus relating to techniques for multi-tile memory management. In an
example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader …
example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader …
Instructions and logic to perform floating point and integer operations for machine learning
One embodiment provides for a graphics processing unit to accelerate machine-learning
operations, the graphics processing unit comprising a multiprocessor having a single …
operations, the graphics processing unit comprising a multiprocessor having a single …
Systems and methods for cache optimization
A Koker, J Ray, E Ould-Ahmed-Vall, A Appu… - US Patent …, 2024 - Google Patents
Abstract Systems and methods for cache utilization are disclosed. In one embodiment, a
graphics processor includes processing resources to perform graphics operations and a …
graphics processor includes processing resources to perform graphics operations and a …