Design and evaluation of a near-sensor magneto-electric fet-based event detector
As a recently developed post-CMOS FET, magneto-electric FETs (MEFETs) offer high-speed
and low-power design characteristics for logic and memory applications. In this article, a …
and low-power design characteristics for logic and memory applications. In this article, a …
MeF-RAM: A new non-volatile cache memory based on magneto-electric FET
Magneto-Electric FET (MEFET) is a recently developed post-CMOS FET, which offers
intriguing characteristics for high-speed and low-power design in both logic and memory …
intriguing characteristics for high-speed and low-power design in both logic and memory …
ALCod: Adaptive LDPC coding for 3D NAND flash memory using inter-layer RBER variation
Three-dimensional (3D) NAND flash memory has been frequently utilized in consumer
electronics as a popular storage device. However, data reliability has become an important …
electronics as a popular storage device. However, data reliability has become an important …
Enabling Normally-Off In Situ Computing With a Magneto-Electric FET-Based SRAM Design
As an emerging post-CMOS Field Effect Transistor, magneto-electric field-effect transistors
(MEFETs) offer compelling design characteristics for logic and memory applications, such as …
(MEFETs) offer compelling design characteristics for logic and memory applications, such as …
Hybrid Magneto-electric FET-CMOS Integrated Memory Design for Instant-on Computing
The surge in the number of normally-off power-constraint Internet of Things (IoT) devices in
recent years has amplified the demand for high-performance and energy-efficient in-memory …
recent years has amplified the demand for high-performance and energy-efficient in-memory …
RTFTL: design and implementation of real-time FTL algorithm for flash memory
Q He, G Bian, W Zhang, Z Li - The Journal of Supercomputing, 2022 - Springer
The optimization of traditional FTL (Flash Translation Layer) algorithm is mainly aimed at the
average response time of flash memory read and write operation on a flash chip, because of …
average response time of flash memory read and write operation on a flash chip, because of …
ADAR: Application-Specific Data Allocation and Reprogramming Optimization for 3-D TLC Flash Memory
High bit-density flash memories, such as triple-level cell (TLC) and quad-level cell (QLC),
have been widely used in flash memory-based storage systems, offering significantly high …
have been widely used in flash memory-based storage systems, offering significantly high …
Softssd: Software-defined ssd development platform for rapid flash firmware prototy**
Recently, solid-state drives (SSDs) have been used in a wide range of emerging data
processing systems. Essentially, an SSD is a complex embedded system that involves both …
processing systems. Essentially, an SSD is a complex embedded system that involves both …
SoftSSD: enabling rapid flash firmware prototy** for solid-state drives
Recently, solid-state drives (SSDs) have been used in a wide range of emerging data
processing systems. Essentially, an SSD is a complex embedded system that involves both …
processing systems. Essentially, an SSD is a complex embedded system that involves both …
Novel, parallel and differential synaptic architecture based on NAND flash memory for high-density and highly-reliable binary neural networks
A novel synaptic architecture based on a NAND flash memory structure is proposed as a
high-density synapse capable of exclusive NOR (XNOR) operation for binary neural …
high-density synapse capable of exclusive NOR (XNOR) operation for binary neural …