3D integrated circuit structure, semiconductor device and method of manufacturing same

Multilevel semiconductor device and structure with memory

Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
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3D non-volatile memory with metal silicide interconnect

M Higashitani, P Rabkin - US Patent 8,933,502, 2015 - Google Patents
US8933502B2 - 3D non-volatile memory with metal silicide interconnect - Google Patents
US8933502B2 - 3D non-volatile memory with metal silicide interconnect - Google Patents 3D …
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Semiconductor system and device

Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 9,219,005, 2015 - Google Patents
US9219005B2 - Semiconductor system and device - Google Patents US9219005B2 -
Semiconductor system and device - Google Patents Semiconductor system and device …
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Integrated circuit device and structure

Z Or-Bach, DC Sekar, B Cronquist - US Patent 9,099,526, 2015 - Google Patents
US9099526B2 - Integrated circuit device and structure - Google Patents US9099526B2 -
Integrated circuit device and structure - Google Patents Integrated circuit device and structure …
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3D semiconductor device and structure

Z Or-Bach, B Cronquist - US Patent 10,840,239, 2020 - Google Patents
H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state
components formed in or on a common substrate including semiconductor components …
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3D semiconductor device and structure with back-bias

Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2015 - Google Patents
H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state
devices during manufacture or treatment thereof; Apparatus specially adapted for handling …
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Semiconductor memory device and structure

Z Or-Bach, JW Han - US Patent 11,956,952, 2024 - Google Patents
A device, including: a first structure including first memory cells, the first memory cells
including first transistors; and a second structure including second memory cells, the second …
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3D semiconductor device and structure

Z Or-Bach, B Cronquist, D Sekar - US Patent 8,803,206, 2014 - Google Patents
US8803206B1 - 3D semiconductor device and structure - Google Patents US8803206B1 - 3D
semiconductor device and structure - Google Patents 3D semiconductor device and structure …
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Monolithic three-dimensional semiconductor device and structure

Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2014 - Google Patents
US8754533B2 - Monolithic three-dimensional semiconductor device and structure - Google
Patents US8754533B2 - Monolithic three-dimensional semiconductor device and structure …
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Methods for processing a 3D semiconductor device

Z Or-Bach, B Cronquist - US Patent 10,297,586, 2019 - Google Patents
A method for processing a 3D semiconductor device, the method including: providing a
wafer including a plurality of first dies, the plurality of first dies including a first transistor layer …
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