Speculative read write locks

S Issa, P Romano, T Lopes - Proceedings of the 19th International …, 2018 - dl.acm.org
Hardware Transactional Memory (HTM) has recently entered the realm of mainstream
computing thanks to its integration in processors commercialized by major industrial …

Techniques for Enhancing the Efficiency of Transactional Memory Systems

S Issa - 2018 - diva-portal.org
Transactional Memory (TM) is an emerging programming paradigm that drastically simplifies
the development of concurrent applications by relieving programmers from a major source of …

[PDF][PDF] Speculative Read-write Locks

TJ dos Santos Lopes - 2018 - dpss.inesc-id.pt
Transactional Memory (TM) is a promising abstraction for parallel programming, which has
recently been implemented in hardware by mainstream like Intel and IBM. Hardware …

[PDF][PDF] Hardware Read-Write Lock Elision on Intel Processors

TJ dos Santos Lopes - dpss.inesc-id.pt
Transactional Memory (TM) is a promising alternative to lock-based synchronization
mechanisms. This report analyses the state of art and existing implementations of TM …

Energy-aware scheduling in transactional memory systems

A Marques, A Baldassin - 2016 29th Symposium on Integrated …, 2016 - ieeexplore.ieee.org
Transaction scheduling is a relatively new technique for transactional memory systems
responsible for deciding which transactions to run in a given moment. Current transactional …

CPU-core frequency scaling for efficient thread scheduling in transactional memories

P Di Sanzo, B Ciciani - 2016 International Conference on High …, 2016 - ieeexplore.ieee.org
Transaction Memory systems may suffer from performance degradation when the
concurrency level grows. The transaction abort rate caused by high concurrency may be …

[HENVISNING][C] SCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

SD Yalew - 2018 - KTH Royal Institute of Technology

[HENVISNING][C] Speculative Read-Write Lock Elision

TJ dos Santos Lopes - 2018

[HENVISNING][C] Algorithms for Enhancing the Performance Robustness of Transactional Memory Systems

NML Diegues - 2016 - INSTITUTO SUPERIOR TÉCNICO

[HENVISNING][C] Efficient Software Transactional Memory via Thread Scheduling and Dynamic Voltage and Frequency Scaling

S Conoci - 2017 - Sapienza, University of Rome