Scalable algorithms for molecular dynamics simulations on commodity clusters
Although molecular dynamics (MD) simulations of biomolecular systems often run for days to
months, many events of great scientific interest and pharmaceutical relevance occur on long …
months, many events of great scientific interest and pharmaceutical relevance occur on long …
[BOOK][B] A primer on memory consistency and cache coherence
Many modern computer systems, including homogeneous and heterogeneous architectures,
support shared memory in hardware. In a shared memory system, each of the processor …
support shared memory in hardware. In a shared memory system, each of the processor …
Checkmate: Automated synthesis of hardware exploits and security litmus tests
Recent research has uncovered a broad class of security vulnerabilities in which
confidential data is leaked through programmer-observable microarchitectural state. In this …
confidential data is leaked through programmer-observable microarchitectural state. In this …
MeltdownPrime and SpectrePrime: Automatically-synthesized attacks exploiting invalidation-based coherence protocols
The recent Meltdown and Spectre attacks highlight the importance of automated verification
techniques for identifying hardware security vulnerabilities. We have developed a tool for …
techniques for identifying hardware security vulnerabilities. We have developed a tool for …
A formal analysis of the NVIDIA PTX memory consistency model
D Lustig, S Sahasrabuddhe, O Giroux - Proceedings of the Twenty …, 2019 - dl.acm.org
This paper presents the first formal analysis of the official memory consistency model for the
NVIDIA PTX virtual ISA. Like other GPU memory models, the PTX memory model is weakly …
NVIDIA PTX virtual ISA. Like other GPU memory models, the PTX memory model is weakly …
The Emergence of Hardware Fuzzing: A Critical Review of its Significance
R Saravanan, SMP Dinakarrao - arxiv preprint arxiv:2403.12812, 2024 - arxiv.org
In recent years, there has been a notable surge in attention towards hardware security,
driven by the increasing complexity and integration of processors, SoCs, and third-party IPs …
driven by the increasing complexity and integration of processors, SoCs, and third-party IPs …
A survey of the RISC-V architecture software support
RISC-V is a novel open instruction set architecture that supports multiple platforms while
maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has …
maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has …
Instruction-level abstraction (ila) a uniform specification for system-on-chip (soc) verification
Modern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain
specialized semi-programmable accelerators in addition to programmable processors. In …
specialized semi-programmable accelerators in addition to programmable processors. In …
HMC: Model checking for hardware memory models
Stateless Model Checking (SMC) is an effective technique for verifying safety properties of a
concurrent program by systematically exploring all of its executions. While SMC has been …
concurrent program by systematically exploring all of its executions. While SMC has been …
Synthesizing formal models of hardware from RTL for efficient verification of memory model implementations
Modern hardware complexity makes it challenging to determine if a given microarchitecture
adheres to a particular memory consistency model (MCM). This observation inspired the …
adheres to a particular memory consistency model (MCM). This observation inspired the …