Programming and synthesis for software-defined FPGA acceleration: status and future prospects

YH Lai, E Ustun, S **ang, Z Fang, H Rong… - ACM Transactions on …, 2021 - dl.acm.org
FPGA-based accelerators are increasingly popular across a broad range of applications,
because they offer massive parallelism, high energy efficiency, and great flexibility for …

[ΒΙΒΛΙΟ][B] FPGAs for software programmers

D Koch, F Hannig, D Ziener - 2016 - Springer
Dirk Koch · Frank Hannig Daniel Ziener Editors Page 1 Dirk Koch · Frank Hannig Daniel Ziener
Editors FPGAs for Software Programmers Page 2 FPGAs for Software Programmers Page 3 …

The LEAP FPGA operating system

K Fleming, M Adler - FPGAs for software programmers, 2016 - Springer
FPGAs offer attractive power and performance for many applications, especially relative to
traditional sequential architectures. In spite of these advantages, FPGAs have been …

Enabling effective FPGA debug using overlays: Opportunities and challenges

F Eslami, E Hung, SJE Wilton - arxiv preprint arxiv:1606.06457, 2016 - arxiv.org
FPGAs are going mainstream. Major companies that were not traditionally FPGA-focused
are now seeking ways to exploit the benefits of reconfigurable technology and provide it to …

Signal-tracing techniques for in-system FPGA debugging of high-level synthesis circuits

J Goeders, SJE Wilton - … Aided Design of Integrated Circuits and …, 2016 - ieeexplore.ieee.org
High-level synthesis (HLS) promises to increase designer productivity in the face of
increasing field-programmable gate array sizes, and broaden the market of use, allowing …

A survey on performance optimization of high-level synthesis tools

L Huang, DL Li, KP Wang, T Gao, A Tavares - Journal of computer science …, 2020 - Springer
Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of
the heterogeneous computing. The register transfer level (RTL) design flows demand the …

Leveraging hardware probes and optimizations for accelerating fuzz testing of heterogeneous applications

J Wang, Q Zhang, H Rong, GH Xu, M Kim - Proceedings of the 31st ACM …, 2023 - dl.acm.org
There is a growing interest in the computer architecture community to incorporate
heterogeneity and specialization to improve performance. Developers can create …

Using dynamic signal-tracing to debug compiler-optimized HLS circuits on FPGAs

J Goeders, SJE Wilton - 2015 IEEE 23rd annual international …, 2015 - ieeexplore.ieee.org
High-level synthesis (HLS) for FPGA designs has received considerable attention in recent
years. To make this design methodology mainstream, improved debugging technologies are …

Using source-level transformations to improve high-level synthesis debug and validation on FPGAs

JS Monson, BL Hutchings - Proceedings of the 2015 ACM/SIGDA …, 2015 - dl.acm.org
This paper proposes a method for extending source-level visibility into the RTL of an HLS-
generated design using automated source-level transformations. Using our method, source …

Parallelization and characterization of pattern matching using GPUs

G Vasiliadis, M Polychronakis… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
Pattern matching is a highly computationally intensive operation used in a plethora of
applications. Unfortunately, due to the ever increasing storage capacity and link speeds, the …