Programming and synthesis for software-defined FPGA acceleration: status and future prospects
FPGA-based accelerators are increasingly popular across a broad range of applications,
because they offer massive parallelism, high energy efficiency, and great flexibility for …
because they offer massive parallelism, high energy efficiency, and great flexibility for …
[ΒΙΒΛΙΟ][B] FPGAs for software programmers
Dirk Koch · Frank Hannig Daniel Ziener Editors Page 1 Dirk Koch · Frank Hannig Daniel Ziener
Editors FPGAs for Software Programmers Page 2 FPGAs for Software Programmers Page 3 …
Editors FPGAs for Software Programmers Page 2 FPGAs for Software Programmers Page 3 …
The LEAP FPGA operating system
FPGAs offer attractive power and performance for many applications, especially relative to
traditional sequential architectures. In spite of these advantages, FPGAs have been …
traditional sequential architectures. In spite of these advantages, FPGAs have been …
Enabling effective FPGA debug using overlays: Opportunities and challenges
FPGAs are going mainstream. Major companies that were not traditionally FPGA-focused
are now seeking ways to exploit the benefits of reconfigurable technology and provide it to …
are now seeking ways to exploit the benefits of reconfigurable technology and provide it to …
Signal-tracing techniques for in-system FPGA debugging of high-level synthesis circuits
High-level synthesis (HLS) promises to increase designer productivity in the face of
increasing field-programmable gate array sizes, and broaden the market of use, allowing …
increasing field-programmable gate array sizes, and broaden the market of use, allowing …
A survey on performance optimization of high-level synthesis tools
L Huang, DL Li, KP Wang, T Gao, A Tavares - Journal of computer science …, 2020 - Springer
Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of
the heterogeneous computing. The register transfer level (RTL) design flows demand the …
the heterogeneous computing. The register transfer level (RTL) design flows demand the …
Leveraging hardware probes and optimizations for accelerating fuzz testing of heterogeneous applications
There is a growing interest in the computer architecture community to incorporate
heterogeneity and specialization to improve performance. Developers can create …
heterogeneity and specialization to improve performance. Developers can create …
Using dynamic signal-tracing to debug compiler-optimized HLS circuits on FPGAs
High-level synthesis (HLS) for FPGA designs has received considerable attention in recent
years. To make this design methodology mainstream, improved debugging technologies are …
years. To make this design methodology mainstream, improved debugging technologies are …
Using source-level transformations to improve high-level synthesis debug and validation on FPGAs
This paper proposes a method for extending source-level visibility into the RTL of an HLS-
generated design using automated source-level transformations. Using our method, source …
generated design using automated source-level transformations. Using our method, source …
Parallelization and characterization of pattern matching using GPUs
Pattern matching is a highly computationally intensive operation used in a plethora of
applications. Unfortunately, due to the ever increasing storage capacity and link speeds, the …
applications. Unfortunately, due to the ever increasing storage capacity and link speeds, the …