The use of large language models for code generation is a rapidly growing trend in software
development. However, without effective methods for ensuring the correctness of generated …

Assertion-based verification (ABV) is a critical method for ensuring design circuits comply
with their architectural specifications, which are typically described in natural language. This …

The unprecedented success of Large Language Models (LLMs) like ChatGPT across
diverse domains such as natural language understanding and coding has paved the way for …

Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven
solutions have emerged as formidable tools, yet they typically augment rather than redefine …

This paper presents LLM4S EC HW, a novel framework for hardware debugging that
leverages domain-specific Large Language Model (LLM). Despite the success of LLMs in …

Assertion-based verification (ABV) is a critical method for ensuring design circuits comply
with their architectural specifications, which are typically described in natural language. This …

Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …

In this paper, for the first time, we present a methodology that combines Retrieval
Augmented Generation (RAG) with Large Language Models (LLM) to help with the …

In this paper, we propose a methodology for hardware verification assisted by Large
Language Models (LLMs) in the incremental proof generation process. First, an LLM …

The increasing complexity of modern hardware designs poses significant challenges for
design verification, particularly defining and verifying properties and invariants manually …