Systems on chip (SoC) are becoming increasingly complex, with a large number of
applications integrated on the same chip. Such a system often supports a large number of …

This paper investigates optimized synchronization techniques for shared memory on-chip
multiprocessors (CMPs) based on network-on-chip (NoC) and targeted at future mobile …

Synchronization is of paramount importance to exploit thread-level parallelism on many-core
CMPs. In these architectures, synchronization mechanisms usually rely on shared variables …

While the semiconductor industry has provided us with powerful systems for personal
supercomputing, how to efficiently harness the computing power of these systems still …

A. ABSTRACT Today with the advent of new VLSI processing technologies, System-on-Chip
(SoC) design is gaining prominence in order to achieve faster time to market, reduced costs …

Traditional software-based barrier implementations for shared memory parallel machines
tend to produce hotspots in terms of memory and network contention as the number of …

In this paper we present synchronisation techniques for hard real-time (HRT) capable
execution of parallelised applications on embedded multi-core processors. We show how …

The newly emerging many-core-on-a-chip designs have renewed an intense interest in
parallel processing. By applying Amdahl's formulation to the programs in the PARSEC and …

Barrier synchronization in shared memory parallel machines has been widely implemented
through busy-waiting on shared variables. However, typical implementations of barrier …

We apply the Model-Driven Engineering for adapting User Interfaces (UI) in order to improve
their accessibility into interactive system (IS). The solution that we propose has to be generic …