(51) Int. Cl. A charge trap** floating gate is described with asymmetric GIC I6/06(2006.01)
tunneling barriers. The memory cell includes a source region HOIL 29/788(2006.01) and a …

(57) ABSTRACT A circuit and method for self-converging programming of a charge storage
memory cell. Such as NROM or floating gate flash. The method includes determining a data …

150 disposed above the tunneling dielectric layer. An upper insu lating layer is disposed
above the charge storage layer, and a gate is disposed above the upper insulating multi …

(60) Provisional application No. 60/640.229, filed on Jan. 3, 2005, provisional application
No. 60/647,012, filed (57) ABSTRACT on Jan. 27, 2005, provisional application No. Memory …

2005/0237815 A1 10, 2005 Lue et al. Buckley, J., et al.,“Engineering of Conduction band
Crested Bar 2005/023781.6 A1 10, 2005 Lue et al. riers' or Dielectric Constant Crested …

(57) ABSTRACT A memory cell with a charge trap** structure is pro grammed using refill
cycles that include a program pulse followed by a charge balancing pulse that causes …

(57) ABSTRACT A memory cell with a charge trap** structure has multiple bias
arrangements. Multiple cycles of applying the bias arrangements lowering and raising a …

RE35, 838 E 7, 1998 Momodomi et al. 5,815,441 A* 9/1998 Kobatake............... 365, 18529
5.937, 424 A* 8/1999 Leak et al............. 365,185.33 6,011,725 A 1/2000 Eitan memory arrays …

(57) ABSTRACT A method of operating a memory cell comprises applying a first procedure
(typically erase) to establish a low threshold state including a first bias arrangement causing …

(57) ABSTRACT A vertical channel memory including a substrate, a channel, a multi-layer
structure, a gate, a first terminal and a second terminal is provided. The channel protrudes …