Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …

Modern DRAM cells are periodically refreshed to prevent data loss due to leakage.
Commodity DDR (double data rate) DRAM refreshes cells at the rank level. This degrades …

DRAM has been the dominant technology for architecting main memory for decades. Recent
trends in multi-core system design and large-dataset applications have amplified the role of …

This paper proposes an energy-efficient, high-throughput DRAM architecture for GPUs and
throughput processors. In these systems, requests from thousands of concurrent threads …

Over the past two decades, the storage capacity and access bandwidth of main memory
have improved tremendously, by 128x and 20x, respectively. These improvements are …

Memory bandwidth severely limits the scalability and performance of today's multi-core
systems. Because of this limitation, many studies that focused on improving multi-core …

Although DRAM capacity and bandwidth have increased sharply by the advances in
technology and standards, its latency and energy per access have remained almost …

DRAM is the primary technology used for main memory in modern systems. Unfortunately,
as DRAM scales down to smaller technology nodes, it faces key challenges in both data …

Abstract Graphics Processing Units (GPUs) and other throughput processing architectures
have scaled performance through simultaneous improvements in compute capability and …

High-density DRAM devices spend significant time refreshing the DRAM cells, leading to
performance drop. The JEDEC DDR4 standard provides a Fine Granularity Refresh (FGR) …