A unique feature of this open access textbook is to provide a comprehensive introduction to
the fundamental knowledge in embedded systems, with applications in cyber-physical …

Predicting the number of clock cycles a processor takes to execute a block of assembly
instructions in steady state (the throughput) is important for both compiler designers and …

Analytical databases are continuously adapting to the underlying hardware in order to
saturate all sources of parallelism. At the same time, hardware evolves in multiple directions …

One of the key challenges arising when compilers vectorize loops for today's SIMD-
compatible architectures is to decide if vectorization or interleaving is beneficial. Then, the …

The latest real-time graphics architectures include programmable floating-point vertex and
fragment processors, with support for data-dependent control flow in the vertex processor …

The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-
Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We …

Eight synergistic processor units enable the Cell Broadband Engine's breakthrough
performance. The SPU architecture implements a novel, pervasively data-parallel …

Most implementations of the Single Instruction Multiple Data (SIMD) model available today
require that data elements be packed in vector registers. Operations on disjoint vector …

When vectorizing for SIMD architectures that are commonly employed by today's multimedia
extensions, one of the new challenges that arise is the handling of memory alignment. Prior …

Data locality and parallelism are critical optimization objectives for performance on modern
multi-core machines. Both coarse-grain parallelism (eg, multi-core) and fine-grain …