Chip and package-scale interconnects for general-purpose, domain-specific and quantum computing systems-overview, challenges and opportunities

A Das, M Palesi, J Kim… - IEEE Journal on Emerging …, 2024 - ieeexplore.ieee.org
The anticipated end of Moore's law, coupled with the breakdown of Dennard scaling,
compelled everyone to conceive forthcoming computing systems once transistors reach their …

Survey on terahertz nanocommunication and networking: A top-down perspective

F Lemic, S Abadal, W Tavernier… - IEEE Journal on …, 2021 - ieeexplore.ieee.org
Recent developments in nanotechnology herald nanometer-sized devices expected to bring
light to a number of groundbreaking applications. Communication with and among …

Efficient path profiling

T Ball, JR Larus - Proceedings of the 29th Annual IEEE/ACM …, 1996 - ieeexplore.ieee.org
A path profile determines how many times each acyclic path in a routine executes. This type
of profiling subsumes the more common basic block and edge profiling, which only …

NoC routing protocols–objective-based classification

AB Gabis, M Koudil - Journal of Systems Architecture, 2016 - Elsevier
Abstract NoCs (Network on Chips) are the most popular interconnection mechanism used
for systems that require flexibility, extensibility and low power consumption. However …

Performance evaluation of application map** approaches for network-on-chip designs

W Amin, F Hussain, S Anjum, S Khan, NK Baloch… - IEEE …, 2020 - ieeexplore.ieee.org
Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of
cores on a single system-on-chip (SoC). The dependency on multi-core systems to …

Fault diagnosis and fault-tolerant tracking control for discrete-time systems with faults and delays in actuator and measurement

SY Han, YH Chen, GY Tang - Journal of the Franklin Institute, 2017 - Elsevier
In this paper, the fault diagnosis (FD) and fault-tolerant tracking control (FTTC) problem for a
class of discrete-time systems with faults and delays in actuator and measurement is …

Architecture and advanced electronics pathways toward highly adaptive energy-efficient computing

GP Fettweis, M Dör**haus, J Castrillon… - Proceedings of the …, 2018 - ieeexplore.ieee.org
With the explosion of the number of compute nodes, the bottleneck of future computing
systems lies in the network architecture connecting the nodes. Addressing the bottleneck …

A survey on fault-tolerant application map** techniques for network-on-chip

N Kadri, M Koudil - Journal of Systems Architecture, 2019 - Elsevier
Reliability is becoming a major concern in Networks-on-Chips (NoCs) design. Several
techniques have been proposed in the literature to deal with different types of faults at …

Reliability-aware resource management in multi-/many-core systems: A perspective paper

SS Sahoo, B Ranjbar, A Kumar - Journal of Low Power Electronics and …, 2021 - mdpi.com
With the advancement of technology scaling, multi/many-core platforms are getting more
attention in embedded systems due to the ever-increasing performance requirements and …

Exploring self-repair in a coupled spiking astrocyte neural network

J Liu, LJ McDaid, J Harkin, S Karim… - IEEE transactions on …, 2018 - ieeexplore.ieee.org
It is now known that astrocytes modulate the activity at the tripartite synapses where indirect
signaling via the retrograde messengers, endocannabinoids, leads to a localized self …