2008. O162886 A1 7/2008 Saha et al. 2008, O256073 A1 10, 2008 Detlefset al.
2008/0270745 A1 10, 2008 Saha et al. 2009, OOO6767 A1 1/2009 Saha et al. 2009 …

BACKGROUND In modern computing systems, multiple processors can be present and
each Such processor may execute different threads of code of a common application. To …

7,320,065 B2 1/2008 Gosior cr 7,376,800 B1 5/2008 Choquette (*) Notice: Subject to any
disclaimer, the term of this 7,395,382 B1 7, 2008 Moir patent is extended or adjusted under …

Monitoring performance of one or more architecturally sig nificant processor caches coupled
to a processor. The meth ods include executing an application on one or more proces sors …

BACKGROUND 0002 The ever-increasing gap between processor perfor mance and
memory bandwidth is reflected in the growing timing penalty incurred when a processor …

US PATENT DOCUMENTS 6,438,677 B1 8/2002 Chaudhry et al. 6,457,104 B1 9, 2002
Tremaine et al. 6,587,937 B1 7/2003 Jensen et al. 7,082,601 B2 7/2006 Ohsawa et al …

BACKGROUND Advances in semi-conductor processing and logic design have permitted
an increase in the amount of logic that may be present on integrated circuit devices. As a …

6,751,617 B1 6/2004 Anfindsen 6,842,830 B2 1/2005 Khare 6,845,430 B2 1/2005 Hopeman
data is implemented in a metadata address space while the storage address, when used for …

BACKGROUND Advances in semi-conductor processing and logic design have permitted
an increase in the amount of logic that may be present on integrated circuit devices. As a …

(57) ABSTRACT A memory access command, column address and plurality of write data
values are received within an integrated-circuit memory chip via external signaling links. In …