This paper presents the ITC'02 SOC test benchmarks. The purpose of this new benchmark
set is to stimulate research into new methods and tools for modular testing of SOCs and to …

This paper presents a method to consider a given SOC with pin and peak power constraints,
and simultaneously (1) determine an optimal wrapper width for each core,(2) allocate SOC …

This paper deals with the design of test architectures for modular SOC testing. These
architectures consist of wrappers and TAMs (test access mechanisms). For a given SOC …

We propose an SOC test scheduling method based on simulated annealing. In our method,
the test scheduling is formulated as a two-dimensional bin packing problem (rectangle …

This article deals with the design of on-chip architectures for testing large system chips
(SOCs) for manufacturing defects in a modular fashion. These architectures consist of …

A method and apparatus for automated document layout creation is disclosed. In one
embodiment, the method comprises receiving a first layout of document image objects and …

High performance computing is being increasingly utilized in non-traditional circumstances
where it must interoperate with other applications. For example, online visualization is being …

A method, apparatus and article of manufacture for assisting a user with authoring a
multimedia representation of documents. In one embodiment, the method comprises …

In this paper, we propose an effective fusion scheme of visual and auditory modalities to
detect events in sports video. The proposed scheme is built upon semantic shot …

Multilevel test access mechanism (TAM) optimization is necessary for modular testing of
hierarchical systems-on-chip (SOCs) that contain older-generation SOCs as embedded …