Reducing read latency using a pool of processing cores
J Amit, A Lidor, S Marenkov, R Raikhman - US Patent 8,930,633, 2015 - Google Patents
In a read processing storage system, using a pool of CPU cores, the CPU cores are
assigned to process either write operations, read operations, and read and write operations …
assigned to process either write operations, read operations, and read and write operations …
System and apparatus for consolidated dynamic frequency/voltage control
SS Thomson, M Mondal, N Hariharan - US Patent 9,086,883, 2015 - Google Patents
Methods and apparatus for accomplishing dynamic frequency/voltage control between at
least two processor cores in a multi-processor device or system include receiving busy, idle …
least two processor cores in a multi-processor device or system include receiving busy, idle …
Multi-core processor system with thread queue based power management
Y Ishikawa, T Kizu, R Ohyama - US Patent 8,214,679, 2012 - Google Patents
A multi-core processor system includes: a plurality of processor cores; a power supply unit
that stops supplying or supplies power to each of the processor cores individually; and a …
that stops supplying or supplies power to each of the processor cores individually; and a …
Cache-aware adaptive thread scheduling and migration
R Wang, TYC Tai, PS Diefenbaugh… - US Patent …, 2019 - Google Patents
In one embodiment, a processor includes: a plurality of cores each to independently execute
instructions; a shared cache memory coupled to the plurality of cores and having a plurality …
instructions; a shared cache memory coupled to the plurality of cores and having a plurality …
Energy-efficient multi-core processor
WY Lee - US Patent App. 12/200,698, 2010 - Google Patents
Energy-efficient multi-core processor systems are provided. A multi-core processor may
include a plurality of processor cores configured to process a task in parallel and at least …
include a plurality of processor cores configured to process a task in parallel and at least …
Apparatus and methods for adaptive thread scheduling on asymmetric multiprocessor
MW Morrow, M Garg - US Patent 9,043,795, 2015 - Google Patents
BACKGROUND Many portable products, such as cell phones, laptop com puters, personal
data assistants (PDAs) and the like, utilize a processing system that executes programs …
data assistants (PDAs) and the like, utilize a processing system that executes programs …
Task assignment for processor cores based on a statistical power and frequency model
T Rider, L Faivishevsky, I Ljubunicic, S Taite… - US Patent …, 2017 - Google Patents
ABSTRACT A method and apparatus for assigning tasks to processor cores, based on
usage history, to have tasks executed at the highest frequency with the lowest power …
usage history, to have tasks executed at the highest frequency with the lowest power …
Thread aware power management
WR Hannon, DP Larsen, RC Swanson - US Patent 10,386,900, 2019 - Google Patents
In an embodiment, a power management controller is to receive thread information from a
scheduler, where the thread information includes thread priority information for a thread …
scheduler, where the thread information includes thread priority information for a thread …
System-on-chip queue status power management
DL Bouvier, S Sathe - US Patent 8,639,862, 2014 - Google Patents
2. Description of the Related Art Some conventional processors provide a mechanism for
software (SW) to issue speed up or slow down commands to a programmable engine …
software (SW) to issue speed up or slow down commands to a programmable engine …
Method and apparatus for managing power in a multi-core processor
M Priel, A Rozen, L Smolyansky - US Patent 9,335,805, 2016 - Google Patents
There is provided a method of managing power in a multi core data processing system
having two or more processing cores, comprising determining usage characteristics for the …
having two or more processing cores, comprising determining usage characteristics for the …