Turnitin
降AI改写
早检测系统
早降重系统
Turnitin-UK版
万方检测-期刊版
维普编辑部版
Grammarly检测
Paperpass检测
checkpass检测
PaperYY检测
Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology
Designing a power efficient and high-speed static random-access memory (SRAM) cell with
improved noise stability using traditional complementary metal oxide semiconductor …
improved noise stability using traditional complementary metal oxide semiconductor …
Hybrid-type CAM design for both power and performance efficiency
YJ Chang, YH Liao - IEEE transactions on very large scale …, 2008 - ieeexplore.ieee.org
Content-addressable memory (CAM) is a hardware table that can compare the search data
with all the stored data in parallel. Due to the parallel comparison feature where a large …
with all the stored data in parallel. Due to the parallel comparison feature where a large …
Energy-efficient and variability-resilient 11T SRAM design using data-aware read–write assist (DARWA) technique for low-power applications
The need for power-efficient devices, such as smart sensor nodes, mobile devices, and
portable digital gadgets, is markedly increasing and these devices are becoming commonly …
portable digital gadgets, is markedly increasing and these devices are becoming commonly …
One-sided Schmitt-Trigger-based low power read decoupled 11T CNTFET SRAM with improved stability
The power requirements of wireless sensor networks and internet of things (IoT) applications
heavily rely on batteries. It is crucial that the memory cells utilized in these applications must …
heavily rely on batteries. It is crucial that the memory cells utilized in these applications must …
AWARE (asymmetric write architecture with redundant blocks): A high write speed STT-MRAM cache architecture
Spin-transfer torque magnetic RAM (STT-MRAM) is a promising memory technology for
lower level caches because of its high density and nonvolatile nature. However, the high …
lower level caches because of its high density and nonvolatile nature. However, the high …
A new single-ended SRAM cell with write-assist
RF Hobson - IEEE Transactions on very large scale integration …, 2007 - ieeexplore.ieee.org
A 6T static random access memory (SRAM) cell with a new write-assist (WA) feature is
presented. The WA technique reduces the problem of writing a" one" through an nMOS pass …
presented. The WA technique reduces the problem of writing a" one" through an nMOS pass …
High density and low leakage current based SRAM cell using 45 nm technology
S Akashe, S Sharma - International Journal of Electronics, 2013 - Taylor & Francis
This article is based on the observation of a Complementary Metal-Oxide Semiconductor
(CMOS) five-transistor Static Random Access Memory (SRAM) cell (5T SRAM cell) for very …
(CMOS) five-transistor Static Random Access Memory (SRAM) cell (5T SRAM cell) for very …
A novel 8T SRAM cell with improved read-SNM
A Sil, S Ghosh, M Bayoumi - 2007 IEEE Northeast Workshop on …, 2007 - ieeexplore.ieee.org
As the MOSFET's channel length is scaling down, SRAM stability becomes the major
concern for future technology. The cell becomes more susceptible to both process induced …
concern for future technology. The cell becomes more susceptible to both process induced …
[PDF][PDF] High density and low leakage current based 5T SRAM cell using 45 nm technology
S Akashe, S Bhushan, S Sharma - Romanian journal of information …, 2012 - romjist.ro
This paper is based on the observation of a CMOS five-transistor SRAM cell (5T SRAM cell)
for very high density and low power applications. This cell retains its data with leakage …
for very high density and low power applications. This cell retains its data with leakage …
A proposed SRAM cell for low power consumption during write operation
Purpose–Low power static‐random access memories (SRAM) has become a critical
component in modern VLSI systems. In cells, the bit‐lines are the most power consuming …
component in modern VLSI systems. In cells, the bit‐lines are the most power consuming …