Adaptive queued locking for control of speculative execution
SC Chen, A Kleen - US Patent 10,191,784, 2019 - Google Patents
Adaptive queued locking for control of speculative execu tion is disclosed. An example
apparatus includes a queue controller to control removal of threads from a queue that …
apparatus includes a queue controller to control removal of threads from a queue that …
Two-level scheduler for multi-threaded processing
One embodiment of the present invention sets forth a tech nique for Scheduling thread
execution in a multi-threaded processing environment. A two-level Scheduler maintains a …
execution in a multi-threaded processing environment. A two-level Scheduler maintains a …
Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution
A Gara, M Ohmacht - US Patent 8,838,906, 2014 - Google Patents
In a multiprocessor System with at least two levels of cache, a speculative thread may run on
a core processor in parallel with other threads. When the thread seeks to do a write to main …
a core processor in parallel with other threads. When the thread seeks to do a write to main …
Concurrent scheduling of plan operations in a virtualized computing environment
A portion of the disclosure of this patent document may contain material, which is subject to
copyright protection. The owner has no objection to the facsimile reproduction by any one of …
copyright protection. The owner has no objection to the facsimile reproduction by any one of …
Execution context trace for asynchronous tasks
JJ Karppanen - US Patent 9,582,312, 2017 - Google Patents
BACKGROUND Generally described, software applications include executable code to
implement various processes associated with the Software application. It is common for …
implement various processes associated with the Software application. It is common for …
Managing task dependency within a data processing system
AS Christensen, S Ellis… - US Patent App. 12 …, 2011 - Google Patents
Inventors: Aske Simon Christensen, Trondheim (NO); Sean Ellis A processing apparatus
includes task manager circuitry 14 Farnham (GB); An dreas s issuing task specifiers to …
includes task manager circuitry 14 Farnham (GB); An dreas s issuing task specifiers to …
Method and system for accelerating task control flow
A computing device (eg, a mobile computing device, etc.) may be configured to may be
configured to better exploit the concurrency and parallelism enabled by modern …
configured to better exploit the concurrency and parallelism enabled by modern …
Method and apparatus for downgrading firmware in a controller
YF Wang, MS Gilstrap - US Patent 8,869,131, 2014 - Google Patents
(65) Prior Publication Data(57) ABSTRACT US 2012/0317562 A1 Dec. 13, 2012 A method
for downgrading firmware in a controller is pro (51) Int. Cl. vided. The method includes …
for downgrading firmware in a controller is pro (51) Int. Cl. vided. The method includes …
Methods and apparatus to compile instructions for a vector of instruction pointers processor architecture
YM Astigeyevich, DM Maslennikov… - US Patent …, 2015 - Google Patents
Methods, apparatus, systems, and articles of manufacture to compile instructions for a vector
of instruction pointers (VIP) processor architecture are disclosed. An example method …
of instruction pointers (VIP) processor architecture are disclosed. An example method …
Map** virtual addresses to different physical addresses for value disambiguation for thread memory access requests
A Gala, M Ohmacht - US Patent 8,832,415, 2014 - Google Patents
A multiprocessor system includes nodes. Each node includes a data path that includes a
core, a TLB, and a first level cache implementing disambiguation. The system also includes …
core, a TLB, and a first level cache implementing disambiguation. The system also includes …