Design and Implementation of High Speed Carry Look-Ahead Decimal Adder (CLDA) Using CMOS Technology

A Al Share, O Al-Khaleel, FN Zghoul… - IEEE …, 2025 - ieeexplore.ieee.org
Decimal arithmetic is gaining more attention by researchers due to their importance in many
human-centric applications. Hardware implementations of decimal arithmetic are preferable …

New dual-Vth assignment technique for design of low power CMOS adder

K Fakir, SS Mande - International Journal of Power …, 2024 - inderscienceonline.com
A novel design of sensitivity-based dual threshold voltage (Vth) full adder circuit is presented
in this paper. Transistors of conventional CMOS full adder circuit are assigned with dual-Vth …

Design of energy-efficient and high-speed hybrid decimal adder

N Mashayekhi, G Jaberipur… - The Journal of …, 2025 - Springer
Decimal computations have attracted a lot of attentions in computer science in recent years
due to the increasing significance of decimal-based financial and commercial applications …

Manipulating Band-to-Band Tunneling Current in Low-Voltage pMOS Devices in BCD Technology: A TCAD and Experimental Investigation

G Albani, E Rebussi, E D'Ambrosio… - … on Electron Devices, 2024 - ieeexplore.ieee.org
This study investigates the issue of reducing band-to-band leakage current in low-voltage
(LV) CMOS devices realized using BCD technology. Through TCAD simulations and …

A novel hybrid static offset voltage calibration technique for dynamic comparators using bulk voltage and shunt current trimming techniques

FN Zghoul, TSA Mansour - Integration, 2025 - Elsevier
In this paper, a new hybrid digitally controlled circuit technique is proposed to calibrate the
static offset voltage in the preamplifier stage for the Strong-Arm latch-based dynamic …

Design and analysis of 1-bit hybrid full adder cells for fast computation

A Anand, S Dhariwal, VK Lamba… - International Journal of …, 2024 - Taylor & Francis
This research article introduces a 1-bit Full Adder (FA) cell comprising 20 transistors,
employing Gate Diffusion Input (GDI) and transmission gate logic. The FA cell is segmented …

Design and Analysis of Compact BCD Adder for Future High-Speed and Low-Power Electronic Applications

KU Sri, M Badhshah, J Ajayan - 2024 4th International …, 2024 - ieeexplore.ieee.org
In this study, a unique design of BCD adder optimized for area and speed is proposed. The
design is assessed in comparison to current techniques, with an emphasis on important key …

Quantum-dot Cellular Automata technology to implement digital circuits

SM Nandini, KL Sudha - 2024 2nd International Conference on …, 2024 - ieeexplore.ieee.org
Quantum-dot Cellular Automata (QCA) presents an innovative approach to computing,
utilizing quantum dots for binary operations instead of traditional transistors. The inherent …

A Novel Hybrid Technique for Static Offset Voltage Calibration in Dynamic Comparators Leveraging Bulk Voltage and Shunt Current Trimming

F Nessir Zghoul, T Mansour, G Latif - Takwa and alghazo, jaafar and … - papers.ssrn.com
In this paper, a new hybrid digitally controlled circuit technique is proposed to calibrate the
static offset voltage in the preamplifier stage for the Strong-Arm latch-based dynamic …