A survey on techniques for improving the energy efficiency of large-scale distributed systems

AC Orgerie, MD Assuncao, L Lefevre - ACM Computing Surveys (CSUR), 2014 - dl.acm.org
The great amounts of energy consumed by large-scale computing and network systems,
such as data centers and supercomputers, have been a major source of concern in a society …

A detailed and flexible cycle-accurate network-on-chip simulator

N Jiang, DU Becker, G Michelogiannakis… - … analysis of systems …, 2013 - ieeexplore.ieee.org
Network-on-Chips (NoCs) are becoming integral parts of modern microprocessors as the
number of cores and modules integrated on a single chip continues to increase. Research …

Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

R Marculescu, UY Ogras, LS Peh… - … on computer-aided …, 2008 - ieeexplore.ieee.org
To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

Energy-and performance-aware map** for regular NoC architectures

J Hu, R Marculescu - … Transactions on computer-aided design of …, 2005 - ieeexplore.ieee.org
In this paper, we present an algorithm which automatically maps a given set of intellectual
property onto a generic regular network-on-chip (NoC) architecture and constructs a …

Orion: A power-performance simulator for interconnection networks

HS Wang, X Zhu, LS Peh, S Malik - 35th Annual IEEE/ACM …, 2002 - ieeexplore.ieee.org
We present Orion, a power-performance interconnection network simulator that is capable of
providing detailed power characteristics, in addition to performance characteristics, to …

Energy-aware map** for tile-based NoC architectures under performance constraints

J Hu, R Marculescu - Proceedings of the 2003 Asia and South Pacific …, 2003 - dl.acm.org
In this paper, we present an algorithm which automatically maps the IPs/cores onto a
generic regular Network on Chip (NoC) architecture such that the total communication …

[CARTE][B] Three-dimensional integrated circuit design

VF Pavlidis, I Savidis, EG Friedman - 2017 - books.google.com
Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more
than twice as much new content, adding the latest developments in circuit models …

Performance evaluation of cloud-based log file analysis with Apache Hadoop and Apache Spark

I Mavridis, H Karatza - Journal of Systems and Software, 2017 - Elsevier
Log files are generated in many different formats by a plethora of devices and software. The
proper analysis of these files can lead to useful information about various aspects of each …

" It's a small world after all": NoC performance optimization via long-range link insertion

UY Ogras, R Marculescu - … on very large scale integration (VLSI …, 2006 - ieeexplore.ieee.org
Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication
problems. The NoC communication architectures considered so far are based on either …

ViChaR: A dynamic virtual channel regulator for network-on-chip routers

CA Nicopoulos, D Park, J Kim… - 2006 39th Annual …, 2006 - ieeexplore.ieee.org
The advent of deep sub-micron technology has recently highlighted the criticality of the on-
chip interconnects. As diminishing feature sizes have led to increases in global wiring …