We present a novel clock synchronization algorithm and prove tight upper and lower bounds
on the worst-case clock skew that may occur between any two participants in any given …

We present a novel partially synchronous system model, which augments the asynchronous
model by a (possibly unknown) bound Θ on the ratio of longest and shortest end-to-end …

Clock synchronization is one of the most basic building blocks for many applications in
computer science and engineering. The purpose of clock synchronization is to provide the …

Classic distributed computing abstractions do not match well the reality of digital logic gates,
which are the elementary building blocks of Systems-on-Chip (SoCs) and other Very Large …

This paper provides description and analysis of a new clock synchronization algorithm for
synchronous and partially synchronous systems with unknown upper and lower bounds on …

Today's hardware technology presents a new challenge in designing robust systems. Deep
submicron VLSI technology introduces transient and permanent faults that were never …

Due to their handshake-based flow control, asynchronous circuits generally do not suffer
from metastability issues as much as synchronous circuits do. We will show, however, that …

In this paper, we introduce the Asynchronous Bounded-Cycle (ABC) model, which
considerably relaxes the Theta-Model proposed by Le Lann and Schmid. The ABC model …

Recently we introduced an abstraction method for parameterized model checking of
threshold-based fault-tolerant distributed algorithms. We showed how to verify distributed …

In this paper the authors introduce a novel approach for the on-chip generation of a fault-
tolerant clock. The authors motivate why it becomes more and more desirable to provide …