A survey of research and practices of network-on-chip

T Bjerregaard, S Mahadevan - ACM Computing Surveys (CSUR), 2006 - dl.acm.org
The scaling of microchip technologies has enabled large scale systems-on-chip (SoC).
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …

Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

R Marculescu, UY Ogras, LS Peh… - … on computer-aided …, 2008 - ieeexplore.ieee.org
To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

[BOOK][B] On-chip communication architectures: system on chip interconnect

S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Key research problems in NoC design: a holistic perspective

UY Ogras, J Hu, R Marculescu - Proceedings of the 3rd IEEE/ACM/IFIP …, 2005 - dl.acm.org
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex
on-chip communication problems. The lack of an unified representation of applications and …

A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip

T Bjerregaard, J Sparso - Design, Automation and Test in …, 2005 - ieeexplore.ieee.org
On-chip networks for future system-on-chip designs need simple, high performance
implementations. In order to promote system-level integrity, guaranteed services (GS) need …

Linear-programming-based techniques for synthesis of network-on-chip architectures

K Srinivasan, KS Chatha… - IEEE Transactions on Very …, 2006 - ieeexplore.ieee.org
Application-specific system-on-chip (SoC) design offers the opportunity for incorporating
custom network-on-chip (NoC) architectures that are more suitable for a particular …

A low latency router supporting adaptivity for on-chip interconnects

J Kim, D Park, T Theocharides… - Proceedings of the …, 2005 - dl.acm.org
The increased deployment of System-on-Chip designs has drawn attention to the limitations
of on-chip interconnects. As a potential solution to these limitations, Networks-on-Chip …

A gracefully degrading and energy-efficient modular router architecture for on-chip networks

J Kim, C Nicopoulos, D Park, V Narayanan… - ACM SIGARCH …, 2006 - dl.acm.org
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip
(SoC) designs supporting numerous homogeneous and heterogeneous functional blocks …

System-level buffer allocation for application-specific networks-on-chip router design

J Hu, UY Ogras, R Marculescu - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
In this paper, a novel system-level buffer planning algorithm that can be used to customize
the router design in networks-on-chip (NoCs) is presented. More precisely, given the traffic …

An energy-efficient reconfigurable circuit-switched network-on-chip

PT Wolkotte, GJM Smit, GK Rauwerda… - 19th IEEE International …, 2005 - ieeexplore.ieee.org
Network-on-chip (NoC) is an energy-efficient on-chip communication architecture for multi-
tile system-on-chip (SoC) architectures. The SoC architecture, including its run-time …