Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters
NA Kumari, P Prithvi - Microelectronics Journal, 2022 - Elsevier
In this paper, DC and analog/RF figures of merit (FOMs) for different geometrical variations
of the Gate all around (GAA) Nanosheet FET (NSFET) are computationally examined. For …
of the Gate all around (GAA) Nanosheet FET (NSFET) are computationally examined. For …
Effect of temperature on performance of 5-nm node silicon nanosheet transistors for analog applications
This work investigates the effects of temperature on the performance of a 5-nm node N-
channel Nanosheet Transistor (NST) for analog applications. A fully calibrated commercial …
channel Nanosheet Transistor (NST) for analog applications. A fully calibrated commercial …
Innovative Spacer material integration in Tree-FETs for enhanced performance across Variable channel lengths
D Parvathi, P Prithvi - Micro and Nanostructures, 2024 - Elsevier
This work presents a novel three-channel Tree-FET optimized for superior DC and analog
performance metrics. The device structure features nanosheets with a width (NS WD) of 9 …
performance metrics. The device structure features nanosheets with a width (NS WD) of 9 …
Performance analysis of nanosheet transistor with drain/source extension and high-k spacer optimizations for analog applications
This work proposes an optimized Nanosheet Transistor (NSHT) with an inner high-k spacer
and an underlap region. A symmetric dual-k spacer structure and an undoped underlap …
and an underlap region. A symmetric dual-k spacer structure and an undoped underlap …
Dielectric engineering to suppress cell-to-cell programming voltage interference in 3D NAND flash memory
WJ Jung, JY Park - Micromachines, 2021 - mdpi.com
In contrast to conventional 2-dimensional (2D) NAND flash memory, in 3D NAND flash
memory, cell-to-cell interference stemming from parasitic capacitance between the word …
memory, cell-to-cell interference stemming from parasitic capacitance between the word …
Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology
Y Liu, M Yin, H Zhou, Y You, W Zhang… - … Transactions on Very …, 2025 - ieeexplore.ieee.org
Nanosheet FETs (NSFETs) are considered promising candidates to replace FinFETs as the
dominant devices in sub-5-nm processes. To encourage further research into NSFET-based …
dominant devices in sub-5-nm processes. To encourage further research into NSFET-based …
Effect of process-induced variations on analog performance of silicon based nanosheet transistor
The reliability of Silicon-based nanosheet transistors (NSTs) is limited by process-induced
variations (PIVs) like work-function-variations (WFV), line-edge-roughness (LER), gate-edge …
variations (PIVs) like work-function-variations (WFV), line-edge-roughness (LER), gate-edge …
Performance Analysis of Nanosheet Transistors for Analog ICs
The art of creating nanoscale semiconductor devices has been one of the most advanced
technologies for almost half a century. Metal–oxide–semiconductor field‐effect transistor …
technologies for almost half a century. Metal–oxide–semiconductor field‐effect transistor …
Nanosheet Transistor with Inter-bridge Channels for Superior Delay Performance: A Comparative Study
This paper investigates structural optimization techniques using the high-k spacer and inter-
bridge Silicon (Si)-channels for superior delay performance in Silicon-based nanosheet …
bridge Silicon (Si)-channels for superior delay performance in Silicon-based nanosheet …
Power supply variations and analog performance of 5-nm node silicon Nanosheet transistor
This work estimates the possible changes in analog performance due to on-chip power
supply variations for a 5 nm node N-channel Nanosheet Transistor. A fully calibrated …
supply variations for a 5 nm node N-channel Nanosheet Transistor. A fully calibrated …