Shared memory consistency models: A tutorial

SV Adve, K Gharachorloo - computer, 1996 - ieeexplore.ieee.org
The memory consistency model of a system affects performance, programmability, and
portability. We aim to describe memory consistency models in a way that most computer …

Verification techniques for cache coherence protocols

F Pong, M Dubois - ACM Computing Surveys (CSUR), 1997 - dl.acm.org
In this article we present a comprehensive survey of various approaches for the verification
of cache coherence protocols based on state enumeration,(symbolic model checking, and …

Herding cats: Modelling, simulation, testing, and data mining for weak memory

J Alglave, L Maranget, M Tautschnig - ACM Transactions on …, 2014 - dl.acm.org
We propose an axiomatic generic framework for modelling weak memory. We show how to
instantiate this framework for Sequential Consistency (SC), Total Store Order (TSO), C++ …

Repairing sequential consistency in C/C++ 11

O Lahav, V Vafeiadis, J Kang, CK Hur… - ACM SIGPLAN Notices, 2017 - dl.acm.org
The C/C++ 11 memory model defines the semantics of concurrent memory accesses in
C/C++, and in particular supports racy" atomic" accesses at a range of different consistency …

[BOK][B] Parallel computer architecture: a hardware/software approach

D Culler, JP Singh, A Gupta - 1999 - books.google.com
The most exciting development in parallel computer architecture is the convergence of
traditionally disparate approaches on a common machine structure. This book explains the …

The Java memory model

J Manson, W Pugh, SV Adve - ACM SIGPLAN Notices, 2005 - dl.acm.org
This paper describes the new Java memory model, which has been revised as part of Java
5.0. The model specifies the legal behaviors for a multithreaded program; it defines the …

Memory consistency and event ordering in scalable shared-memory multiprocessors

K Gharachorloo, D Lenoski, J Laudon… - ACM SIGARCH …, 1990 - dl.acm.org
Scalable shared-memory multiprocessors distribute memory among the processors and use
scalable interconnection networks to provide high bandwidth and low latency …

Weak ordering—a new definition

SV Adve, MD Hill - ACM SIGARCH Computer Architecture News, 1990 - dl.acm.org
A memory model for a shared memory, multiprocessor commonly and often implicitly
assumed by programmers is that of sequential consistency. This model guarantees that all …

Foundations of the C++ concurrency memory model

HJ Boehm, SV Adve - ACM SIGPLAN Notices, 2008 - dl.acm.org
Currently multi-threaded C or C++ programs combine a single-threaded programming
language with a separate threads library. This is not entirely sound [7]. We describe an effort …

[BOK][B] A primer on memory consistency and cache coherence

V Nagarajan, DJ Sorin, MD Hill, DA Wood - 2020 - library.oapen.org
Many modern computer systems, including homogeneous and heterogeneous architectures,
support shared memory in hardware. In a shared memory system, each of the processor …