Benchmark figure of merit extensions for low jitter phase locked loops inspired by new PLL architectures
W Bae - IEEE Access, 2022 - ieeexplore.ieee.org
A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …
powerful indicator to compare and to normalize performance of different PLL designs …
A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH -TDC for Low In-Band Phase Noise
This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …
A 2.4-GHz reference-sampling phase-locked loop that simultaneously achieves low-noise and low-spur performance
Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-
locked clock multipliers have demonstrated some of the lowest jitters for a given power …
locked clock multipliers have demonstrated some of the lowest jitters for a given power …
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …
Reference oversampling PLL achieving− 256-dB FoM and− 78-dBc reference spur
This article presents a low jitter, low power, low reference spur LC oscillator-based reference
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
oversampling digital phase locked loop (OSPLL). The proposed reference oversampling …
A 6.75–8.25-GHz− 250-dB FoM rapid ON/OFF fractional-N injection-locked clock multiplier
A rapid ON/OFF LC-based fractional-N injection-locked clock multiplier (ILCM) is presented.
The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs …
The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs …
A dividerless reference-sampling RF PLL with− 253.5 dB jitter FOM and<-67dBc reference spurs
In the recent past, there have been exciting advances in dividerless PLLs, such as sub-
sampling PLLs (SSPLLs)[1, 2] and injection-locked clock multipliers (ILCMs)[3] that …
sampling PLLs (SSPLLs)[1, 2] and injection-locked clock multipliers (ILCMs)[3] that …
A 2.5–5.6 GHz subharmonically injection-locked all-digital PLL with dual-edge complementary switched injection
A 2.5-5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital
phase-locked loop with a dual-edge complementary switched injection technique is …
phase-locked loop with a dual-edge complementary switched injection technique is …
A 1.2 ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique
This paper presents a fully-synthesizable fractional-N injection-locked PLL in 65 nm CMOS.
A true arbitrary non-linearity calibration scheme is specifically proposed for synthesizable …
A true arbitrary non-linearity calibration scheme is specifically proposed for synthesizable …
A 2.25–2.7 GHz area-efficient subharmonically injection-locked fractional-N frequency synthesizer with a fast-converging correlation loop
YH Tseng, CW Yeh, SI Liu - … on Circuits and Systems I: Regular …, 2016 - ieeexplore.ieee.org
An area-efficient subharmonically injection-locked fractional-N frequency synthesizer is
presented. The phase domain analysis confirms that a second-order subharmonically …
presented. The phase domain analysis confirms that a second-order subharmonically …