Superhydrophobic transparent glass (Stg) thin film articles
T Aytug, JT Simpson, DK Christen - US Patent 8,741,158, 2014 - Google Patents
5,510,323 A 4, 1996 Kamo et al. 6,884,527 B2 4/2005 Groves et al. 5,543,630 A 8, 1996
Bliss et al. 6,890.369 B2 5/2005 Goyal et al. 5,650,378 A 7/1997 Iijima et al. 6,899.928 B1 …
Bliss et al. 6,890.369 B2 5/2005 Goyal et al. 5,650,378 A 7/1997 Iijima et al. 6,899.928 B1 …
High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor
Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory
bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material …
bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material …
Method of fabricating a ferroelectric capacitor
S Sun - US Patent 9,111,944, 2015 - Google Patents
US9111944B2 - Method of fabricating a ferroelectric capacitor - Google Patents
US9111944B2 - Method of fabricating a ferroelectric capacitor - Google Patents Method of …
US9111944B2 - Method of fabricating a ferroelectric capacitor - Google Patents Method of …
Composition for forming an optically transparent, superhydrophobic coating
JT Simpson, LA Lewis - US Patent 9,221,076, 2015 - Google Patents
(57) ABSTRACT A composition for producing an optically clear, well bonded
Superhydrophobic coating includes a plurality of hydropho bic particles comprising an …
Superhydrophobic coating includes a plurality of hydropho bic particles comprising an …
High-density low voltage non-volatile differential memory bit-cell with shared plate line
Described is a low power, high-density non-volatile differential memory bit-cell. The
transistors of the differential memory bit-cell can be planar or non-planer and can be …
transistors of the differential memory bit-cell can be planar or non-planer and can be …
Anti-fingerprint coatings
T Aytug, JT Simpson - US Patent 11,292,919, 2022 - Google Patents
An article having a nanostructured surface and a method of making the same are described.
The article can include a substrate and a nanostructured layer bonded to the substrate. The …
The article can include a substrate and a nanostructured layer bonded to the substrate. The …
Stacked ferroelectric non-planar capacitors in a memory bit-cell
A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a
planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C …
planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C …
Semiconductor memory device
R Fukuda, D Takashima - US Patent 7,697,318, 2010 - Google Patents
A memory cell array includes a plurality of memory cells arranged at intersections of bit line
pairs and word lines. Each memory cell includes a first transistor having one main electrode …
pairs and word lines. Each memory cell includes a first transistor having one main electrode …
High-density low voltage non-volatile differential memory bit-cell with shared plate-line
Described is a low power, high-density non-volatile differential memory bit-cell. The
transistors of the differential memory bit-cell can be planar or non-planer and can be …
transistors of the differential memory bit-cell can be planar or non-planer and can be …
Memory array
A memory array has a multiplicity of row conductors and a multiplicity of column conductors,
the row conductors and column conductors being arranged to cross at cross-points, and has …
the row conductors and column conductors being arranged to cross at cross-points, and has …